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Senior Design Engineer

162241
Hyderabad, India, India
Jan 10, 2022

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Job Description

Description

At Xilinx, we are leading the industry transformation to build an adaptable, intelligent world. ARE YOU bold, collaborative, and creative? We develop leaders and innovators who want to revolutionize the world of technology. We believe that by embracing diverse ideas, pushing boundaries, and working together as ONEXILINX, anything is possible.

Our culture of innovation began with the invention of the Field Programmable Gate Array (FPGA), and with the 2018 introduction of our Adaptive Compute Acceleration Platform (ACAP), has made a quantum leap in capability, solidifying our role as the adaptable platform supplier of choice. From the beginning, we have always believed in providing inventors with products and platforms that are infinitely adaptable. From self-driving cars, to world-record genome processing, to AI and big data, to the world's first 5G networks, we empower the world's builders and visionaries whose ideas solve every day problems and improve people's lives.

If you are PASSIONATE, ADAPTABLE, and INNOVATIVE, Xilinx is the right place for you! At Xilinx, we care deeply about creating significant development experiences while building a strong sense of belonging and connection. We champion an environment of empowered learning, wellness, community engagement, and recognition, so you can focus on work that matters - world class technology that improves the way we live and work. We are ONEXILINX.

Education Requirements

  • B.Tech or M.Tech in Electrical Engineering, Computer Engineering or related field

Years of Experience

  • B.Tech w/6+ years or M.Tech w/4+ years experience in Electrical Engineering, Computer Engineering or related field
  • Desired skills
    • RTL design, timing constraints and design methodologies
    • Design qualification – RTL-DRC, STA, CDC, RDC, Constraints checking
    • Programming experience – Perl, TCL, Python
    • Design verification – Verilog simulation, coverage analysis, assertions
    • Prior knowledge of Scan design, ATPG, Memory BIST, Repair and harvesting for yield are a plus

Job Description

  • Develop IPs and methodologies for Xilinx’ next generation SoCs
  • Define constraints and dependencies for IPs based on block interfaces, power supply & configuration requirements
  • Optimize overall product cost by modeling and analyzing die vs test costs
  • Contribute to DFx Architecture for Xilinx’s next generation monolithic and stacked SoC product families
  • Work with functional IP teams on integration, analysis and qualification methodologies for a growing number of IPs, tools and flows
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