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FDST Verification group is looking for a Staff Design Verification Engineer to provide technical leadership, contribution on FPGA block, sub-system and full chip verification. The individual will help design, develop and use simulation and/or formal based verification environments, at block, sub system and full chip FPGA level, to prove the functional correctness of FPGA SoCs. The ideal candidate is one who has a proven track record on driving strategies and successful verification execution on high performance IPs and/or SoC designs. Candidate is expected to be a strong team player with good communication and leadership skills and one who is able to positively and
strategically influence the FPGA design teams with an eye towards improving overall product quality.