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Staff Design Verification Engineer - FPGA SOC

162233
Singapore, Singapore, Singapore
Jan 13, 2022

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Job Description

Description

At Xilinx, we are leading the industry transformation to build an adaptable, intelligent world. ARE YOU bold, collaborative, and creative? We develop leaders and innovators who want to revolutionize the world of technology. We believe that by embracing diverse ideas, pushing boundaries, and working together as ONEXILINX, anything is possible.

Our culture of innovation began with the invention of the Field Programmable Gate Array (FPGA), and with the 2018 introduction of our Adaptive Compute Acceleration Platform (ACAP), has made a quantum leap in capability, solidifying our role as the adaptable platform supplier of choice. From the beginning, we have always believed in providing inventors with products and platforms that are infinitely adaptable. From self-driving cars, to world-record genome processing, to AI and big data, to the world's first 5G networks, we empower the world's builders and visionaries whose ideas solve every day problems and improve people's lives.

If you are PASSIONATE, ADAPTABLE, and INNOVATIVE, Xilinx is the right place for you! At Xilinx, we care deeply about creating significant development experiences while building a strong sense of belonging and connection. We champion an environment of empowered learning, wellness, community engagement, and recognition, so you can focus on work that matters - world class technology that improves the way we live and work. We are ONEXILINX.

FDST Verification group is looking for a Staff Design Verification Engineer to provide technical leadership, contribution on FPGA block, sub-system and full chip verification. The individual will help design, develop and use simulation and/or formal based verification environments, at block, sub system and full chip FPGA level, to prove the functional correctness of FPGA SoCs. The ideal candidate is one who has a proven track record on driving strategies and successful verification execution on high performance IPs and/or SoC designs. Candidate is expected to be a strong team player with good communication and leadership skills and one who is able to positively and
strategically influence the FPGA design teams with an eye towards improving overall product quality.

  • Bachelor's Degree w/ 8+ years or MS w/ 5+ years or PhD w/ 3+ years in Electrical Engineering, Computer Engineering, or Computer Science.
  • 3+ years of experience managing verification teams.
  • Requires proven track record in technical leadership. This includes planning, execution, tracking, verification closure, and delivery to programs.
  • Requires strong experience with development of UVM, OVM, VMM and/or Verilog, SystemVerilog test benches for full chip testbench and usage of simulation tools/debug environments like Synopsys VCS, Cadence IES to test full chip FPGA fabric and SoCs.
  • Requires strong understanding of state of the art of verification techniques, including assertion and metric-driven verification.
  • Verification experience in MathEngine/DSP optimized for wireless applications, AXI, NoC, HBM, DDR4, PCIe verification is a plus.
  • Verification experience in full chip verification is a plus.
  • Familiarity with verification management tools as well as understanding of database management particularly as it pertains to regression management is a plus.
  • Strong understanding of different phases of ASIC and/or full custom chip development is required.
  • Experience in modeling SystemC and using SystemC based models in verification is a plus.
  • Experience with FPGA programming and software is a plus.
  • Verification experience in PCIe, Processors, Graphics is a plus.
  • Experience with formal property checking tools such as Cadence (IEV), Jasper, and Synopsys (Magellan) is a plus.
  • Experience with gate level simulation, power verification, reset verification, contention checking, abstraction techniques is a plus.
  • Some DFX/DFT and UPF/Power-Aware simulation experience is a plus.
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