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The Xilinx Central Engineering Memory Subsystem team is searching for a passionate, adaptable and innovative design engineer to contribute towards the next generation of HBM PHY and more.
Xilinx has an opening for a Senior Hardware Design Engineer in the IP Design team. This position entails working on digital IC design development of PHY and integration of Memory subsystem blocks for next generation FPGAs. Candidate will support varied aspects of the entire design process including RTL design and functional verification, FE design flows and/or synthesis, timing closure, supporting SW views and working with test engineers on silicon verification and characterization.
- The candidate will be responsible for different design stages in the RTL to GDS implementation.
- The candidate will design, implementation RTL for complex digital and analog blocks using Verilog/System Verilog.
- The candidate will be responsible for physical design flows (synthesis with DFT) and work on Static Timing Analysis.
- The candidate will work closely with Functional Verification teams to support block level verification (constrained-random and/or directed verification environments using System Verilog and UVM).
- The candidate is expected to have strong scripting skills in Perl, Tcl, Shell and/or other languages to support existing & develop new design automation tools/flows for the varied aspects of the design implementation.
- The candidate is expected to work with various design groups across different disciplines in different geographical locations.
- The candidate is expected to have regular communication with project teams worldwide to resolve issues and ensure targeted goals.
- BS with 3+ or MS with 1+ or PhD in Electrical Engineering, Computer Engineering or related equivalent
- RTL design implementation of Digital blocks using Verilog/System Verilog.
- Knowledge in VLSI design, Design Automation, IC design.
- Basic knowledge of EDA Tools (like Synopsys DC Compiler, Primetime, VCS, Cadence Virtuoso).
- Knowledge of Physical Design (floor planning, synthesis, place & route) and Static Timing Analysis is preferred.
- Experience with UVM/OVM and/or Verilog, System Verilog test benches, BFMs and usage of simulation tools/debug environments is preferred.
- Basic understanding of FPGA architecture and customer usage model is a plus.
- Knowledge of Cadence SPICE, IC compiler is a plus.
- Experience with Silicon debug/validation at the tested and board level is a plus.
- Proficiency in Perl, Tcl, Shell, Python and/or other scripting language.
- Experience creating internal and/or customer facing detailed documentation.
- Excellent written and verbal communication skills in English.
- Self-motivated team worker with ability to work in a fast-paced work environment.