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Xilinx is looking for a talented individual to join the high speed memory interfaces design engineering group, in the position of Senior Design Engineer to work on the modelling of next generation memory controllers and network on a chip bus.
The successful candidate will work as a contributing member responsible for the architecture and design of next generation memory controller models for Xilinx customers. Responsibilities include System Verilog/System C coding, architecting, implementing, documenting and validating the models. The area of focus would be on controllers like DDR4, DDR5, LPDDR4, LPDDR5 & HBM. The candidate must have excellent inter-personal and communication skills and be able to work independently.
Xilinx holds a strong position in the FPGA all programmable paradigm. This position offers candidates exposure to the latest generation IP, tools, boards, FPGA products and the ability to design and develop high speed memory IP cores.