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As a member of the SoC Physical Integration team, you'll interface with various engineering groups, including architecture, design, CAD, software, and product engineering, across various geographies and drive different aspects of the physical/electrical verification and tape out of Xilinx SoC FPGA/ACAP devices. Common essential duties and responsibilities may include, but are not limited to:
- Owning the definition and development of flows and methodologies for chip level integration
- Driving development of design tools/flows to improve verification and/or efficiency
- Designing (RTL and custom), verifying, and integrating FPGA/ACAP sub-blocks
- Coordinating activities between different design groups to ensure smooth integration
- Evaluating chip level architectures and providing feedback from the physical integration point of view
- Executing chip level physical verification
- Executing chip level electrical verification
- Understanding of FPGA architecture and overall design flows/methodologies
- Advanced knowledge/experience with design and verification tools such as Virtuoso and Calibre
- Knowledge of and/or experience with P&R tools
- Solid background in fundamental circuit design including experience with Spice/Verilog
- Semiconductor device physics knowledge is a plus
- Strong debug skills and ability to drive issues to closure
- Moderate to advanced scripting experience using Perl, Python, TCL, C-shell, Make and/or other scripting languages
- Good knowledge and experience with basic Unix data management and job control
- Excellent written and oral communication skills
- Must be a team player