This exciting position is in Xilinx DCG - Alveo, Compute Platforms, and Infrastructure (ACPI) Engineering group as the Senior RTL Design Engineer. It will provide the individual with an opportunity to build a strong technical career in Xilinx next generation Hard/Soft IP Design. Join us on our journey in developing world class Soft IP solutions for the next generation of Xilinx highly flexible and adaptive FPGAs.
As an Senior RTL Design Engineer you will work as part of a team responsible for IP/Systems design focused primarily on AXI4 based solutions. RTL Design Engineers are expected to have thorough understanding of the AXI4 protocol, participate in providing inputs during solution architecture, Micro-architecting, RTL designing & developing IPs/Systems.
This position requires the individual to be creative, team-oriented, technology savvy, able to come up with real world use case scenarios for designing the solutions and ensure high quality & high performance solution delivery to customers.
A major part of your responsibility will be to take an independent design role in product/IP micro-architecture definition and RTL design including:
- Understanding product specifications and deriving the module level architecture
- Evaluating high level architecture to a implementation feasibility level
- Derive the product metrics (performance, latency etc.) & ensuring micro-architecture to ensure the performance requirement
- Defining micro-architecture, designing, documentation, prototyping - Interact with internal stakeholder teams as necessary
- Evaluating and executing design and development plans for IPs
- Working with cross functional teams in reviewing the verification and validation plans and ensure the product delivered is of high quality
- Contributing to process improvement in design and development methodologies that impact the productivity
- Proficiency in Verilog RTL coding and RTL methodologies
- Knowledge of Vivado, FPGA boards & AXI4 protocols
- Strong oral and written communication skills are essential
- Ability to work collaboratively with other engineers and have good ownership and leadership skills
- Good understanding of system design aspects and its impact on performance and throughput
- Experience in Soft IP RTL development, system level verification, validation and on board debugging
- Familiarity with testing on-board & debugging with system ILA’s/ on-chip debugging tools
- The ideal candidate should be a proactive contributor and subject matter expert
Education and Experience
- A minimum of 5-6 years of relevant experience is required.
- A Bachelor/Master Degree in Electrical or Electronics or VLSI engineering
- Ability to work independently in developing complex Soft RTL IPs
Key areas of expertise:
- AXI4 Protocol
- Verilog RTL coding
- System, IP and micro-architecture design