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RTL Design Engineer 2

161947
Hyderabad, India, India
Nov 30, 2021

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Job Description

Description

Job Summary

This exciting position in the Xilinx Data Center Storage IP and Solutions Engineering group as the RTL Design Engineer will provide the individual with an opportunity to build a strong technical career in Xilinx next generation Hard & Soft Storage & networking IP Design. Join us on our journey in developing world class Hard & Soft IP solutions for the next generation of Xilinx highly flexible and adaptive FPGAs in the Storage & Networking space.
As a RTL Design Engineer you will work as part of a team responsible for IP/Systems design in the data center storage & netowrking domain. RTL Design Engineers are expected to have thorough understanding of the Data Center Storage and networking standards, participate in Micro-architecting, RTL designing & developing IPs/Systems.
This position requires the individual to be creative, team-oriented, technology savvy, able to come up with real world use case scnearios for designing the solutions and ensure high quality & high performance solution delivery to customers 

Essential Functions: 
    A major part of your responsibility will be to take a role in product/IP micro-architecture definition and RTL designing in the Data Center Storage & Networking IP/Systems development including: 
    - Understanding product specifications and deriving the module level micro-architecture
    - Working with leads to derive the product metrics (performance, latency etc.) & ensuring micro-architecture to ensure the performance requirement
    - Participating in u-Architecture, designing, documentation, prototyping - Interact with internal stakeholder teams as necessary
    - Evaluating and executing design and development plans for IPs 
    - Working with cross functional teams in reviewing the verification and validation plans and ensure the product delivered is of high quality
    - Contributing to process improvement in design and development methodologies that impact the productivity 

Job Requirement:          
    - Proficiency in RTL coding and RTL methodologies
    - Strong oral and written communication skills are essential
    - Ability to work collaboratively with other engineers and have good ownership and leadership skills
    - Detailed understanding and proven track record of designing leading edge standard and proprietary high speed interfaces like Storage IPs/Solutions, PCIe, Ethernet
    - Good understanding of system design aspects and its impact on performance and throughput
    - Experience in Si RTL IP development, system level verification, validation and debugging 
    - Familiarity with electrical challenges that come with high speed link design & testing on-board 
    - Knowledge of storage, networking and Ethernet protocols
    - The ideal candidate should be a proactive contributor 

 

Qualifications:

Education and Experience           
    - A minimum of 3 years of relevant experience is required. 
    - A Bachelor/Master Degree in Electrical or Electronics or VLSI engineering 
    - Ability to work independently in developing complex Si RTL IPs
    
Key areas of expertise:
    - NVMe, RDMA based product 
    - PCIe Product

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