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Senior DFT Verification Engineer

161913
Hyderabad, India, India
Nov 21, 2021

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Job Description

Description

At Xilinx, we are leading the industry transformation to build an adaptable, intelligent world. ARE YOU bold, collaborative, and creative? We develop leaders and innovators who want to revolutionize the world of technology. We believe that by embracing diverse ideas, pushing boundaries, and working together as ONEXILINX, anything is possible.

Our culture of innovation began with the invention of the Field Programmable Gate Array (FPGA), and with the 2018 introduction of our Adaptive Compute Acceleration Platform (ACAP), has made a quantum leap in capability, solidifying our role as the adaptable platform supplier of choice. From the beginning, we have always believed in providing inventors with products and platforms that are infinitely adaptable. From self-driving cars, to world-record genome processing, to AI and big data, to the world's first 5G networks, we empower the world's builders and visionaries whose ideas solve every day problems and improve people's lives.

If you are PASSIONATE, ADAPTABLE, and INNOVATIVE, Xilinx is the right place for you! At Xilinx, we care deeply about creating significant development experiences while building a strong sense of belonging and connection. We champion an environment of empowered learning, wellness, community engagement, and recognition, so you can focus on work that matters - world class technology that improves the way we live and work. We are ONEXILINX.

 

Responsibilities include the following:

  • Will be leading a team of verification engineers in Xilinx India, and work with a cross geographical teams to verify the next generation MPSOC DFX architecture
  • Work with DFX Architecture, DFX Implementation and design teams to drive the verification of all DFX features like SCAN, MBIST, LBIST and JTAG
  • Actively participate in the architectural discussions and provide feedback to design and architecture teams as needed  
  • Develop scalable verification platform in System Verilog / UVM. Able to guide team in writing assertions and checkers.
  • Be responsible for a comprehensive verification plan and drive the implementation of verification test
  • Responsible for SCAN, MBIST, IJTAG and JTAG verification
  • Responsible for SCAN, MBIST, IJTAG and JTAG gate-level simulations

 

 

  • Bachelors or Masters in electrical or computer engineering
  • 12+ total of which 4+ years of experience in the verification of DFX architectures and features
  • Experience in specifying and developing the verification infrastructure for verifying DFX features
  • Strong foundation in SoC DFX architecture and verification of DFX features in multi-IP designs
  • Strong analytical problem solving, and attention to details 
  • Strong experience in HDL, verification, and general computational logic design/verification concepts
  • Expertise in Verilog/System Verilog, UVM, Scripting languages like Perl/Python, etc.
  • Excellent written and verbal communication skills
  • Excellent interpersonal skills, self-motivated
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