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Senior Product Engineer - FPGA and ACAP Implementation Tools

161911
Longmont, CO, United States
Nov 22, 2021

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Job Description

Description

The Senior Product Management Engineer position is in the FPGA Implementation Software group, located in San Jose (California) or Longmont (Colorado), for an application engineer to focus on place-and-route tools feature roadmap definition, specification, validation, documentation, train the trainer material and key customers support. Under the supervision of experienced Product Engineers, the successful candidate will work closely with several R&D teams, internal application design teams and tier-1 customers to improve FPGA compilation software quality of results and ease of use in order to enable the next generation of designs across the UltraScale and Versal ACAP device families. Daily activities will include the following duties:

  • Deep-diving on new and critical tool issues seen by Vivado users internally and externally to identify work-arounds and future enhancements. Triaging reported issues in several Vivado product areas, such as flow, IDE, synthesis, implementation, netlist and device models, and help engineering address them effectively.
  • Actively exploring innovative methodologies and their impact on flow and design practices, with emphasis on synthesis (C/C++/RTL), logic optimization, placement, routing, timing closure, compile time.
  • Owning a Vivado product area, tracking product development schedules and issues, and validating the readiness of new or enhanced features in any new Vivado release.
  • Working closely with Xilinx Business Units (Data Center, Wired, Wireless, Emulation & Prototyping, Test Equipment) to improve their designs, products and customer experience.
  • Developing and delivering training materials on new features and methodologies.
  • Authoring high quality documentation tuned to the needs of the reader for their areas of expertise
  • Staying current with and proposing the internal use of industry approaches, algorithms, and practices

 

MS+6 or BS+8 or equivalent work experience in Electrical Engineering or similar technology area.

  • Customer Awareness: Has excellent working knowledge of RTL-based design flows and expectations.
  • Product Knowledge: Has good working knowledge of the entire FPGA or ASIC design process and tool flow, with basic understanding in timing analysis and closure. Scripting experience (Tcl, Perl, Python) is desired.
  • Design Enablement: Has good understanding of design methodologies for timing closure and runtime reduction.
  • Problem Solving: Ability to handle and solve complex system level issues.
  • Technical Communication: Can simplify and communicate even the most complex subjects, making options, tradeoffs, and impact clear.

 

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