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Senior RTL Design Engineer

161900
San Jose, CA, United States
Nov 18, 2021

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Job Description

Description

At Xilinx, we are leading the industry transformation to build an adaptable, intelligent world. ARE YOU bold, collaborative, and creative? We develop leaders and innovators who want to revolutionize the world of technology. We believe that by embracing diverse ideas, pushing boundaries, and working together as ONEXILINX, anything is possible.

Our culture of innovation began with the invention of the Field Programmable Gate Array (FPGA), and with the 2018 introduction of our Adaptive Compute Acceleration Platform (ACAP), has made a quantum leap in capability, solidifying our role as the adaptable platform supplier of choice. From the beginning, we have always believed in providing inventors with products and platforms that are infinitely adaptable. From self-driving cars, to world-record genome processing, to AI and big data, to the world's first 5G networks, we empower the world's builders and visionaries whose ideas solve every day problems and improve people's lives.

If you are PASSIONATE, ADAPTABLE, and INNOVATIVE, Xilinx is the right place for you! At Xilinx, we care deeply about creating significant development experiences while building a strong sense of belonging and connection. We champion an environment of empowered learning, wellness, community engagement, and recognition, so you can focus on work that matters - world class technology that improves the way we live and work. We are ONEXILINX.

Description

Xilinx SERDES team develops high-performance, multi-protocol wireline transceivers in state-of-the-art CMOS processes. We are seeking a SERDES physical layer (PHY) design engineer to join our world-class team. The job responsibilities include the following:

  • RTL design of digital blocks such as calibration loops, clock-and-data recovery (CDR), equalization adaptation loops, and digital signal processing (DSP) block
  • Working with system architecture, verification, DFT, timing, PnR, and validation teams to perform pre-TO design sign-off and to bring up silicon
  • Micro-architecture:  contribute or lead to deliver power and area efficient implementations of required silicon functionality

Qualification

This position requires M.S. in electrical engineering, computer engineering, or closely related fields, with relevant project/internship experience.

Successful candidates need to demonstrate the following

  • Project/internship/work experience in implementing digital blocks through RTL design, preferably having completed at least one cycle of Synthesis and Place-and-Route of a digital circuit block.
  • Strong teamwork and communication skills
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