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Senior Application Engineer

161898
San Jose, CA, United States
Nov 22, 2021

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Job Description

Description

Xilinx is looking for a talented and self-driven individual to join the Wired IP Solutions Group (WISG) in the position of Senior Applications Engineer. In this role, you will work alongside our Customers who are developing next-generation Networking products.  Additionally, you will have the opportunity to engage in IP testing, training of field engineers and creating proof-of-concept demonstrations.  Your role will allow you to engage in projects spanning our entire product portfolio including high speed Ethernet IP, Time Sensitive Networking IP, and high-speed Network Security IP.  As part of our team, Xilinx will provide the training necessary to help our customers bring ACAP(FPGA) solutions to the market.

The successful candidate will have demonstrated their ability to quickly grasp new networking technologies and solve multi-dimensional problems, either through their industry experience or during their course work. Further, the candidate will have shown the ability to drive projects to successful outcomes within team and individual environments.

Experience with Verilog RTL coding is a must. Experience in Software development using C or Python and Scripting languages is preferred.  It is also desirable for applicants to have experience with wired communications protocols, FPGA architecture and design, and ASIC EDA design flows. A working knowledge of test and verification strategies would be an asset.     

In addition to strong technical abilities, the position requires excellent written and verbal communication skills that will be utilized for multi-location collaboration and understanding customer specifications.

We are building the next generation of Networks. Xilinx already holds a leading position in the wired infrastructure manufacturing industry and is driving the ‘programmable imperative’ into all areas of advanced networking systems. This job opening presents an opportunity to work with a highly motivated team, best-in-class configurable silicon and software and industry leading wired communications technologies.

 

Job Requirements

  • BSEE minimum required.
  • +5 years ASIC/FPGA design, verification, or IP applications.
  • Experience in Verilog or System Verilog, SW experience with C, Python.
  • Knowledge of wired communication standards including: Ethernet, OTN, MACsec, IPsec, TLS.
  • Experience in ASIC/FPGA design and verification flows.
  • Excellent written and verbal communication skills. 

Desired Skills

  • Familiarity with Networking Timing Protocols (TSN, PTP) and applications.
  • Experience in product documentation, product guides and user guides
  • Experience in working with customers in support calls involving technical debug
  • Experience with Lab testing of new or prototype devices or systems.
  • Experience with Xilinx tools and flow.
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