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Staff SOC Integration Design Engineer

161885
San Jose, CA, United States
Nov 25, 2021

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Job Description

Description

At Xilinx, we are leading the industry transformation to build an adaptable, intelligent world. ARE YOU bold, collaborative, and creative? We develop leaders and innovators who want to revolutionize the world of technology. We believe that by embracing diverse ideas, pushing boundaries, and working together as ONEXILINX, anything is possible.

Our culture of innovation began with the invention of the Field Programmable Gate Array (FPGA), and with the 2018 introduction of our Adaptive Compute Acceleration Platform (ACAP), has made a quantum leap in capability, solidifying our role as the adaptable platform supplier of choice. From the beginning, we have always believed in providing inventors with products and platforms that are infinitely adaptable. From self-driving cars, to world-record genome processing, to AI and big data, to the world's first 5G networks, we empower the world's builders and visionaries whose ideas solve every day problems and improve people's lives.

If you are PASSIONATE, ADAPTABLE, and INNOVATIVE, Xilinx is the right place for you! At Xilinx, we care deeply about creating significant development experiences while building a strong sense of belonging and connection. We champion an environment of empowered learning, wellness, community engagement, and recognition, so you can focus on work that matters - world class technology that improves the way we live and work. We are ONEXILINX.

Xilinx has an opening for a Staff SOC Integration Design Engineer in the SOC Design team. This team is responsible for designing the Processor Sub-system for the Adaptable Compute Acceleration Platform (ACAP).

 

In this highly visible role, you will:

  • Own the design and implementation of blocks to meet functional, timing, area and power requirements
  • Guide and review verification for these blocks
  • Design and implement logic functions that enable efficient test and debug
  • Participate in silicon bring-up for features owned
  • Implement Automation to increase design team efficiency
  • Participate in build management

  • Required Qualifications
    • MSEE with 8 years of experience or equivalent
    • Experience in designing blocks for an SOC
    • Experience in integrating ASIC IP into SOC
    • Experience writing timing constraints and exceptions in TCL or SDC syntax
    • Experience with automation using scripting techniques such as PERL, Python or TCL
    • Experience running standard quality checks such as Lint and CDC
    • Experience designing with multiple power domains including writing UPF
    • Simulation experience and experience building block level verification suites
    • Experience with synthesis, static timing analysis & optimization
    • Ability to develop clear and concise engineering documentation
    • Ability to lead others, junior engineers or cross functional teams, through complex activities
    • Experience with industry-standard EDA tools from Cadence, Synopsys or Mentor
    • Excellent verbal and written communication skills
    • Excellent organizational skills and attention to detail

 

  • Desired Qualifications
    • Understanding of ARM architecture and APB, AXI, CHI protocols
    • Understanding of coherent mesh network (CMN) designs
    • Understanding of crypto algorithms like AES, SHA, RSA, and ECDSA
    • Understanding of design for security best practices
    • Understanding of design for Functional Safety best practices
    • Experience running automated quality checks on timing constraints
    • MBIST, LBIST, Scan, Scan Compression, ATPG and JTAG design
    • Experience working in design teams distributed over multiple sites
    • Post-silicon validation and debug experience
    • FPGA knowledge and emulation experience
    • Xilinx ISE or Vivado Design Suite and Xilinx Embedded Development Kit
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