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Product Engineer for FPGA and ACAP Compilation Tools

161727
Hyderabad, India, India
Nov 25, 2021

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Job Description

Description

Xilinx Hyderabad is looking for a self-motivated engineer to work on RTL synthesis and implementation analysis, design tuning and timing closure for FPGAs. We are looking for smart, creative people who have a passion for solving complex problems.  

The ideal candidate should have a strong background in RTL design using Verilog/VHDL and exposure to timing closure with foundations in timing analysis & digital design. The candidate should have a solid understanding of timing constraints, RTL coding styles and applications. Daily duties include the following: 

  • Explore critical tool issues seen by internal IP teams or customers and help identify workarounds and future enhancements 

  • Tracking, prioritizing, and assigning reported tool issues to the appropriate engineering teams 

  • Adopt proper tool methodology, and illustrate best practices via examples, tutorials and demos 

  • Identify, document and present new design techniques leading to higher productivity or higher performance 

  • Staying current with and proposing the internal use of industry approaches, algorithms, and practices 

 

Required Education and Experience:   

  • BS or MS in EE or CE with 3+ years of experience in digital design and/or timing closure  

  • Strong background in RTL design using Verilog/VHDL  

  • Timing Constraints (SDC) & Static Timing Analysis  

  • Strong understanding and usage of ASIC and/or FPGA software tool chain  

  • Strong Digital Design Fundamentals and applications  

  • Scripting languages such as TCL, Perl or Python  

Preferred Experience: Exposure to any of these areas:   

  • Applications and Designs in Wireless/Wired domain 

 

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