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IC Layout Engineer-SGUnited Mid-Career Pathways Programme

161740
Singapore, Singapore, Singapore
Nov 8, 2021

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Job Description

Description

At Xilinx, we are leading the industry transformation to build an adaptable, intelligent world. ARE YOU bold, collaborative, and creative? We develop leaders and innovators who want to revolutionize the world of technology. We believe that by embracing diverse ideas, pushing boundaries, and working together as ONEXILINX, anything is possible.

Our culture of innovation began with the invention of the Field Programmable Gate Array (FPGA), and with the 2018 introduction of our Adaptive Compute Acceleration Platform (ACAP), has made a quantum leap in capability, solidifying our role as the adaptable platform supplier of choice. From the beginning, we have always believed in providing inventors with products and platforms that are infinitely adaptable. From self-driving cars, to world-record genome processing, to AI and big data, to the world's first 5G networks, we empower the world's builders and visionaries whose ideas solve every day problems and improve people's lives.

If you are PASSIONATE, ADAPTABLE, and INNOVATIVE, Xilinx is the right place for you! At Xilinx, we care deeply about creating significant development experiences while building a strong sense of belonging and connection. We champion an environment of empowered learning, wellness, community engagement, and recognition, so you can focus on work that matters - world class technology that improves the way we live and work. We are ONEXILINX.

This position reports to Engineer Manager and focuses on FPGA physical implementation in advanced technolgy nodes. Layout is extremely challenging at these smaller process nodes. Project tasks will include: layout of analog and digital circuits. There is the opportunity to contribute to methodology initiatives to accelerate design layout.

 

The successful incumbent should be/possess the following:

  • At least 2 years of analog custom IC physical design experience
  • Experience with schematic-driven layout, floor planning, chip level routing, design for manufacturing and design rule and connectivity verification is preferred
  • Understanding of silicon process technologies 
  • Hands-on experience using Cadence and Mentor tools is preferred
  • Strong debug capabilities with parasitic extraction, LVS/DRC and other Physical verification checks.
  • Familiarity with circuit design concepts, flow and IC manufacturing processes

Duration of attachment: Up to 6months

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