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Xilinx is looking for a talented individual to join the DFE Technology team in the position of Sr Verification Engineer. This team develops high performance and low cost digital front end (DFE) Radio designs for 5G base stations and DOCSIS Remote-PHY applications with Xilinx’s unique RFSoC, RFSOC DFE and Versal products and influences future device architectures. As Sr. Verification Engineer, you will have the opportunity to work on, architect verification methodologies and develop test benches to simulate Wireless IP, Digital Front End Sub-systems for 4G, 5G Communication Systems.
- Develop verification methodologies and design, implement test environments to verify wireless IP and DFE Sub-systems.
- Review IP feature specifications, interface specifications and make use of Design Review meetings to develop Test plan targeting functional Coverage, Code Coverage and false tolerant scenarios.
- Maintain and enhance existing test environments to meet all quality check requirements.
- Candidate will participate in different phases of IP verification like Design feature and interface reviews, Test plan development, establishing infrastructure for automation of daily regression, Functional/Code coverage report generation, debug issues faced by customers and suggest testcase correction if needed.
- Work with geographically distributed teams, lead verification activities and obtain good understanding of dependencies to re-prioritize the tasks accordingly.
- Responsible for writing Matlab based test scenarios to configure and analyze DSP block’s performance in simulations.
- Conduct Quality check-list inspections and build/lead a verification team.
Technical Skill Requirements:
- Master’s/Bachelor’s degree in Electronics and Communication Engineering or equivalent preferred.
- 8+ years of experience as Verification engineer.
- 6+ years of hands on experience in developing test-benches using System-Verilog, for modules with standard interfaces like AXI4-Lite, AXI-Stream, SPI, I2C etc.
- 4+ years of hands on experience in developing test-plans, creating test-bench drives to generate control and data sequence procedures, getting 100% functional/Code coverage.
- Hand on experience in System level debugging and test case triaging followed by blame finding is a must.
- Must have strong competency in developing test-benches using System-Verilog and strong understanding of verification methodologies like UVM/VMM is a plus.
- Understanding of formal verification/assertions, LINT and CDC tool is mandatory.
- Strong understanding of automation scripts like Shell, Bash, Perl, Tcl and Python are must.
- Matlab coding and generation of input/output reference stimulus using Matlab scripts is a plus.
- Excellent documentation, presentation and communications skills.