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HW Design Engineer

161527
Hyderabad, India, India
Nov 2, 2021

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Job Description

Description

At Xilinx, we are leading the industry transformation to build an adaptable, intelligent world. ARE YOU bold, collaborative, and creative? We develop leaders and innovators who want to revolutionize the world of technology. We believe that by embracing diverse ideas, pushing boundaries, and working together as ONEXILINX, anything is possible.

Our culture of innovation began with the invention of the Field Programmable Gate Array (FPGA), and with the 2018 introduction of our Adaptive Compute Acceleration Platform (ACAP), has made a quantum leap in capability, solidifying our role as the adaptable platform supplier of choice. From the beginning, we have always believed in providing inventors with products and platforms that are infinitely adaptable. From self-driving cars, to world-record genome processing, to AI and big data, to the world's first 5G networks, we empower the world's builders and visionaries whose ideas solve every day problems and improve people's lives.

If you are PASSIONATE, ADAPTABLE, and INNOVATIVE, Xilinx is the right place for you! At Xilinx, we care deeply about creating significant development experiences while building a strong sense of belonging and connection. We champion an environment of empowered learning, wellness, community engagement, and recognition, so you can focus on work that matters - world class technology that improves the way we live and work. We are ONEXILINX.

Job Description 

Xilinx is looking for a talented individual to join the DFE Technology team in the position of HW Design Engineer. This team develops high performance and low cost digital front end (DFE) Radio designs for 5G base stations and DOCSIS Remote-PHY applications with Xilinx’s unique RFSoC and Versal products and influences future device architectures. As HW Design Engineer, you will have the opportunity to work on Wireless/Wired Communication systems and design/implement building blocks required for Digital Front End for these Communication systems.

Key Responsibilities:

  • Implement and optimize signal processing blocks using VHDL.   
  • Responsible for Implementation, testing of communication signal processing algorithms with Matlab reference models.
  • Execute module level and system level verification/validation of signal processing blocks. Develop test plan to get functional and code coverage.
  • Develop module level test benches using System-Verilog.
  • Work within the team to define detailed design requirements and perform design optimizations for performance, resource/timing/power.
  • Responsible for writing Matlab based test scenarios to configure and analyze DSP block’s performance on FPGA evaluation platform.
  • Develops innovative but practical solutions to advanced technical problems in engineering.         
  • Create internal facing detailed documentation (micro-architecture design documents, test specifications, test reports, etc.). 

Technical Skill Requirements: 

  • Master’s/Bachelor’s degree in Electronics and Communication Engineering or equivalent preferred.
  • 3+ years of implementing Signal processing designs.
  • 2+ years of hands on experience in implementing signal processing blocks on FPGAs.
  • 1+ years of hands on experience on fixed-point optimization and resource optimization of signal processing blocks.   
  • Hands on experience in designing and implementing Digital Signal Processing blocks using VHDL/Verilog.
  • Must have strong competency in simulating complex communication and signal processing algorithms.
  • Practical experience with designing the 5G wireless solutions a definite plus.
  • Understanding of data interfacing protocols AXI-Stream, AXI, I2C, SPI etc is mandatory.
  • Experience in validation with Emulators and FPGA evaluation boards is highly desirable. 
  • Demonstrable proficiency with scripting language like Perl/Python/Tcl is required.
  • Excellent documentation, presentation and communications skills.
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