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Senior STA Engineer

161276
Hyderabad, India, India
Oct 1, 2021

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Job Description

Description

At Xilinx, we are leading the industry transformation to build an adaptable, intelligent world. ARE YOU bold, collaborative, and creative? We develop leaders and innovators who want to revolutionize the world of technology. We believe that by embracing diverse ideas, pushing boundaries, and working together as ONEXILINX, anything is possible.

Our culture of innovation began with the invention of the Field Programmable Gate Array (FPGA), and with the 2018 introduction of our Adaptive Compute Acceleration Platform (ACAP), has made a quantum leap in capability, solidifying our role as the adaptable platform supplier of choice. From the beginning, we have always believed in providing inventors with products and platforms that are infinitely adaptable. From self-driving cars, to world-record genome processing, to AI and big data, to the world's first 5G networks, we empower the world's builders and visionaries whose ideas solve every day problems and improve people's lives.

If you are PASSIONATE, ADAPTABLE, and INNOVATIVE, Xilinx is the right place for you! At Xilinx, we care deeply about creating significant development experiences while building a strong sense of belonging and connection. We champion an environment of empowered learning, wellness, community engagement, and recognition, so you can focus on work that matters - world class technology that improves the way we live and work. We are ONEXILINX.

 

Thorough understanding of complete ASIC timing closure flow with strong STA fundamentals.

Must have gone through multiple SoC tape-out experiences including Timing and Functional ECO cycles.

 

Expertise with industry-standard STA tools like Primetime, PT based TCL scripting is a must

Should have prior experience with block and full-chip constraints development and providing guidance to RTL and PD teams to help meet the timing spec

Should understand the complete physical design aspects/stages related to timing closure.

Hands-on with PnR on few blocks would be helpful.

Good understanding of physical closure, floor plan, CTS, routing, timing, noise, crosstalk, electromigration, IR drop, process variations, characterization, 3D ICs, low power CMOS, digital logic, and circuit design, ASIC/ SOC integration.

After initial flow/methodology ramp-up should be able to operate independently and drive issues to closure working with cross-site and cross-functional teams.

Should be able to drive new flows/methodologies deployment efforts/activities

 

Good verbal and written communication skills are a must.

Should be a very good team player and be able to guide junior engineers on day-to-day issues/problems.

Any experience with technical management would be an added plus.

 

5 - 8 years of relevant experience.

Education à ECE/EE Engineering background, Specialization in VLSI/Semiconductors/Micro-electronics is added plus.

 

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