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Senior Staff Design Engineer - Lead

161214
San Jose, CA, United States
Sep 20, 2021

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Job Description

Description

At Xilinx, we are leading the industry transformation to build an adaptable, intelligent world. ARE YOU bold, collaborative, and creative? We develop leaders and innovators who want to revolutionize the world of technology. We believe that by embracing diverse ideas, pushing boundaries, and working together as ONEXILINX, anything is possible.

Our culture of innovation began with the invention of the Field Programmable Gate Array (FPGA), and with the 2018 introduction of our Adaptive Compute Acceleration Platform (ACAP), has made a quantum leap in capability, solidifying our role as the adaptable platform supplier of choice. From the beginning, we have always believed in providing inventors with products and platforms that are infinitely adaptable. From self-driving cars, to world-record genome processing, to AI and big data, to the world's first 5G networks, we empower the world's builders and visionaries whose ideas solve every day problems and improve people's lives.

If you are PASSIONATE, ADAPTABLE, and INNOVATIVE, Xilinx is the right place for you! At Xilinx, we care deeply about creating significant development experiences while building a strong sense of belonging and connection. We champion an environment of empowered learning, wellness, community engagement, and recognition, so you can focus on work that matters - world class technology that improves the way we live and work. We are ONEXILINX.

Xilinx has an opening for a Hardware Lead Engineer in the SOC Design team. This team is designing the silicon portion of Adaptable Compute Acceleration Platform.

 

In this highly visible role, you will:

  • Work in a cross-functional capacity with multiple teams across geographic locations
  • You will be the micro-architect for new COE blocks of the SoC. This will include advanced elements such as coherent as well as non-coherent interconnects, virtualization, memory protection, advanced CPUs, H/W accelerators and more
  • Work closely with the main architecture team to make architectural trade-offs based on features, performance requirements and system limitations
  • You will be the link between the high-level Architecture and the Design teams, developing and owning the intermediate uArchitecture documentation , as well as mentoring the design engineers
  • Work with several verification and validation teams to help develop testbenches around the COE blocks
  • Collaborate with architecture to develop requirements for performance verification
  • Participate in silicon bring-up for COE blocks
  • Technical individual contributor, with the possibility of managing a small team

Required Qualifications

      • BS with 12+ years of experience OR MS with 8+ years of experience OR PhD with 5+ years of experience in Electrical Engineering or related equivalent
      • Experience in integrating ASIC IP into SOC’s
      • Experience with chip-level integration of design blocks
      • Experience in micro-architecture of complex designs
      • Prior experience with interconnect networks
      • Experience in designing high performance blocks for an SOC
      • Good understanding of ARM AMBA protocols, including AXI&APB
      • Experience running standard quality checks such as Lint and CDC
      • Simulation and associated debug experience
      • Experience with synthesis, static timing analysis & optimization
      • Experience writing timing constraints and exceptions in TCL or SDC syntax
      • Ability to develop clear and concise engineering documentation
      • Experience with industry-standard EDA tools from Cadence, Synopsys and Mentor
      • Excellent verbal and written communication skills
      • Excellent organizational skills and attention to detail
      • Teamplayer

Desired Qualifications

      • Understanding of ARM CPU architectures
      • Prior experience with Cache Coherent Interconnects and protocols such as ARM CHI and ACE
      • Understanding of industry standard communication protocols such as PCIe
      • Experience with multiple power domains including writing UPF
      • Automation experience with scripting languages such as PERL, Python or TCL
      • Experience working in design teams distributed over multiple sites
      • Post-silicon validation and debug experience
      • FPGA knowledge and emulation experience
      • Xilinx ISE or Vivado Design Suite and Xilinx Embedded Development Kit
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