At Xilinx, we are leading the industry transformation to build an adaptable, intelligent world. ARE YOU bold, collaborative, and creative? We develop leaders and innovators who want to revolutionize the world of technology. We believe that by embracing diverse ideas, pushing boundaries, and working together as ONEXILINX, anything is possible.
Our culture of innovation began with the invention of the Field Programmable Gate Array (FPGA), and with the 2018 introduction of our Adaptive Compute Acceleration Platform (ACAP), has made a quantum leap in capability, solidifying our role as the adaptable platform supplier of choice. From the beginning, we have always believed in providing inventors with products and platforms that are infinitely adaptable. From self-driving cars, to world-record genome processing, to AI and big data, to the world's first 5G networks, we empower the world's builders and visionaries whose ideas solve every day problems and improve people's lives.
If you are PASSIONATE, ADAPTABLE, and INNOVATIVE, Xilinx is the right place for you! At Xilinx, we care deeply about creating significant development experiences while building a strong sense of belonging and connection. We champion an environment of empowered learning, wellness, community engagement, and recognition, so you can focus on work that matters - world class technology that improves the way we live and work. We are ONEXILINX.
Role and Responsibilities:
- Responsible for Physical Design from RTL to GDS2 at 7nm technology node.
- Hands on experience in Block level /Top level Floorplan and PNR activities
- Hands on experience in working with latest PNR tool workflows and technology nodes.
- Good control over scripting languages like PERL, TCL and strong debug capabilities
- Ability to debug/workaround and make progress is must
- Hands on experience with physical verification tools is beneficial.
Education Requirements : Master’s/Bachelor’s Degree in Electrical/Electronic engineering
Years of Experience : 12+ years of experience in ASIC Synthesis, Place and Route flows and design closure