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• Power integrity analysis for die package and PCB, which includes but not limited to layout extraction, electromagnetic and HSPICE simulation to meet silicon noise spec and decoupling strategy and analysis.
• Simultaneous switching noise/output (SSN or SSO) analysis for I/O power domain. Eye diagram and jitter analysis via Chip-package-board co-simulation.
• Optimal layer stackup & power plane assignment to minimize voltage noise.
• Special noise-sensitive power supply analysis and layout guideline.
• Signal trace length matching and impact to timing.
• Crosstalk analysis and reduction.
• Full-wave simulation and model extraction for signal integrity and power integrity analysis.
• BS with 5+ years of exp or MS 3+ years of exp or PhD years of exp in Electrical Engineering or Computer Engineering or related equivalent
• Solid background on transmission line theory and in-depth knowledge of electromagnetics, PCB layout and package layout techniques.
• Experience with SI simulation tools, e.g. Synopsis HSPICE, Ansys HFSS, Q3D, Cadence PowerSI, PowerDC, and Agilent ADS.
• Experience with lab measurements using oscilloscopes, TDRs, VNAs, and spectrum analyzers.
• Experience in FPGA design is a plus.
• Self-motivated, teamwork, and good communication skills.
* Understanding system memory IO bus standard - DDR4/5 LPDDR4/5 HBM3 is a plus.