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Standard Cell Library Design Intern

161011
San Jose, CA, United States
Aug 9, 2021

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Job Description

Description

At Xilinx, we are leading the industry transformation to build an adaptable, intelligent world. ARE YOU bold, collaborative, and creative? We develop leaders and innovators who want to revolutionize the world of technology. We believe that by embracing diverse ideas, pushing boundaries, and working together as ONEXILINX, anything is possible.

Our culture of innovation began with the invention of the Field Programmable Gate Array (FPGA), and with the 2018 introduction of our Adaptive Compute Acceleration Platform (ACAP), has made a quantum leap in capability, solidifying our role as the adaptable platform supplier of choice. From the beginning, we have always believed in providing inventors with products and platforms that are infinitely adaptable. From self-driving cars, to world-record genome processing, to AI and big data, to the world's first 5G networks, we empower the world's builders and visionaries whose ideas solve every day problems and improve people's lives.

If you are PASSIONATE, ADAPTABLE, and INNOVATIVE, Xilinx is the right place for you! At Xilinx, we care deeply about creating significant development experiences while building a strong sense of belonging and connection. We champion an environment of empowered learning, wellness, community engagement, and recognition, so you can focus on work that matters - world class technology that improves the way we live and work. We are ONEXILINX.

We are looking for a Standard Cell Library Design Intern to join our team!

Responsibilities include the following: 

  • Perform QA on liberty timing model
  • Perform trend analysis and data mining across releases and technology nodes
  • Help out with circuit checks and analyze trend of Performance/Power/Area scaling
  • Perform block level timing test regression

Education Requirements

Currently, pursuing a MS or Ph.D degree with Electrical Engineering emphasis

Location: In US, prefer to be local to the Bay Area, but not required.

Looking for the candidate to start right away for 3-6 months. Hours are flexible, minimum part-time (20 hours per week) to maximum full-time (40 hours per week).

Experiences:

  • Knowledge of standard cell library common functional offering and basic design
  • Knowledge of liberty timing model a plus
  • Knowledge of RTL Verilog, DFT modeling a plus
  • Understanding of advanced technology node device physics a plus
  • Experience with common scripting languages a plus: Perl, Tcl
  • Experience of using hspice and similar circuit simulators to validate design performance and robustness
  • ASIC design experiences with Synthesis and P&R a plus
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