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AI Accelerator Designer

161005
Beijing Shi, China, China
Aug 23, 2021

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Job Description

Description

At Xilinx, we are leading the industry transformation to build an adaptable, intelligent world. ARE YOU bold, collaborative, and creative? We develop leaders and innovators who want to revolutionize the world of technology. We believe that by embracing diverse ideas, pushing boundaries, and working together as ONEXILINX, anything is possible.

Our culture of innovation began with the invention of the Field Programmable Gate Array (FPGA), and with the 2018 introduction of our Adaptive Compute Acceleration Platform (ACAP), has made a quantum leap in capability, solidifying our role as the adaptable platform supplier of choice. From the beginning, we have always believed in providing inventors with products and platforms that are infinitely adaptable. From self-driving cars, to world-record genome processing, to AI and big data, to the world's first 5G networks, we empower the world's builders and visionaries whose ideas solve every day problems and improve people's lives.

If you are PASSIONATE, ADAPTABLE, and INNOVATIVE, Xilinx is the right place for you! At Xilinx, we care deeply about creating significant development experiences while building a strong sense of belonging and connection. We champion an environment of empowered learning, wellness, community engagement, and recognition, so you can focus on work that matters - world class technology that improves the way we live and work. We are ONEXILINX.

 

AI Accelerator Designer: 

Job Responsibilities: 

  • Be responsibile for AI accelerator architecture design, RTL/HLS/AIE engine coding, test case design and debugging on board

  • Write the specification document for related tasks

  • Optimize the timing/resource/pipeline of the related design

  • Support customer requirements and Vitis AI release.

Job Requirements: 

  • Bachelors or Masters degree in Electronics/Electrical/Computer Engineering.

  • More than 2 years of working experience on FPGA/ASIC design. 

  • Excellent skills in Verilog/C/C++ design

  • Experience with standard protocol and interfaces and IO standards,

  • Good sense of co-working with team members

  • Knowledge of Pyhon, tcl, makefile script language(better)

  • Good understanding of deep learning acceleration(better)

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