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- Help automate and enhance standard cell design model generation and QA, including optimization required in mapping to new technology
- Develop new checks to strengthen stdcell design QA checks
- Participate in setting up and executing stdcell library design regression from RTL, QA to release
- Perform spice based circuit checks for design robustness, and to validate performance change
- Investigate and resolve block level design related issues
Education Requirement: BSEE/MSEE
- Minimum 3 years of standard cell or ASIC design experience.
- Good understanding of library characterization tool Liberate and/or Silicon Smart
- Knowledge of RTL Verilog, DFT modeling
- Understanding of spice netlist and extracted DSPF formats
- Familarity with common standard cell functionality
- In-depth knowledge of timing Liberty format including Power, CCS, Variation Modeling
- Understanding of various library design kit format and generation
- Knowledge of device physics and process
- Experience in Perl automation to qualify standard library design kits
- Understanding of analysis and sign-off tools including LEC, Primetime
- Knowledge of hspice and similar circuit simulators
- Circuit design experience of state-of-the-art standard cells
- Experience in Synthesis using Design Compiler and P&R using ICC2 or Innovus a plus