Xilinx is seeking a Staff SDC timing engineer to develop SDC timing constraints for large SOC’s with multiple physical blocks and 300+ clock domains. The candidate will be responsible for running pre-route timing QC and QoR regressions and resolving SDC issues in the pre-route and post-route implementation. He/She will also support the RTL design team in the RTL handoff process by running additional QC regressions including LINT, DFT DRC, CDC, RDC, CLP, and Fishtail. The candidate will be responsible for driving content owners and managing the overall RTL dashboard cleanup for each RTL handoff milestone.
The position requires a mix of SDC knowledge, EDA tool competence and TCL-based scripting capability (both in EDA tool environments and stand-alone Linux TCL shell scripts). Ideal candidates will not only have extensive SDC development and debug experience, but, also have experience cleaning various RTL quality metrics in complex, hierarchical designs and automating that process for improved efficiency. As a middle end engineer, familiarity with both front end (RTL) flows and backend (Synthesis and P&R) flows is desired.
High energy candidates with strong written and verbal communication skills, and structured, well-organized work habits are encouraged to apply.
Experience with the following is required:
Experience with any of the following is desired:
Shell Scripting Experience:
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|BS with 8+ years of exp or MS with 6+ years of exp or PhD with 3+ years of exp in Electrical Engineering or Computer Engineering or related equivalent|