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Develop and Review Test Plan based on design specification
Develop constrained-Random verification environment for complex DUT
Implement coverage matrix using cover point and assertion
Create and debug tests for DUT
Resolved bugs with remote designers
At least 10 years of hands on experience with SystemVerilog/OVM/UVM
Bachelor/Masters Degree in Electrical/Electronics/Computer Engineering
Strong understanding of verification process from test plan to coverage completion
Strong communication and Analytical skills
Understanding of HDL (Verilog, VHDL)