UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

Networking Timing Solution Architect

160807
Waterloo, Canada, Canada
Oct 19, 2021

Share:

Job Description

Description

***This position can be based in The United States, or Canada***

 

Xilinx is looking for a talented individual to join the Wired IP Solutions Group (WISG) in the position of Networking Timing Solution Architect. The successful candidate will join our development team, creating ASIC and FPGA-based intellectual property and Software to address the needs of state-of-the-art communications systems. 

The demands of 5G wireless and IIoT applications are pushing the bounds of timing accuracy and quality of service within wired communications. The Timing Solution Architect will work with Xilinx’s customers and internal engineering teams to define next generation time distribution IP solutions and Time Sensitive Networking IP.  In addition to leading IP developments, the Architect will engage in proof of concept demonstrations and development of industry standards.

It is expected that the candidate will have had experience in the design and deployment of timing distribution solutions for wireless, transport or other high-accuracy applications.  In addition, candidates should have experience with the design of Time Sensitive Networking (TSN) systems.  Experience should include understanding of the physical elements in such systems (e.g. Oscillators, DLLs) as well as the protocols running over the network (e.g. PTP, time aware QoS).

In addition to strong technical abilities, the position requires excellent written and verbal communication skills that will be utilized for developing design specifications and fostering collaboration. Using these communications skills the candidate would be able to produce reports and presentations to internal and customer audiences or standards bodies. Lastly, the candidate should also have experience leading and mentoring junior engineers, and coordinating engineering tasks.

At Xilinx, we are leading the industry transformation to build an adaptable, intelligent world. ARE YOU bold, collaborative, and creative? We develop leaders and innovators who want to revolutionize the world of technology. We believe that by embracing diverse ideas, pushing boundaries, and working together as ONEXILINX, anything is possible.

Our culture of innovation began with the invention of the Field Programmable Gate Array (FPGA), and with the 2018 introduction of our Adaptive Compute Acceleration Platform (ACAP), has made a quantum leap in capability, solidifying our role as the adaptable platform supplier of choice. From the beginning, we have always believed in providing inventors with products and platforms that are infinitely adaptable. From self-driving cars, to world-record genome processing, to AI and big data, to the world's first 5G networks, we empower the world's builders and visionaries whose ideas solve every day problems and improve people's lives.

If you are PASSIONATE, ADAPTABLE, and INNOVATIVE, Xilinx is the right place for you! At Xilinx, we care deeply about creating significant development experiences while building a strong sense of belonging and connection. We champion an environment of empowered learning, wellness, community engagement, and recognition, so you can focus on work that matters - world class technology that improves the way we live and work. We are ONEXILINX.

 

Education Requirements

  • BSEE minimum required.

Years of Experience

  • 15+ years digital design and/or software design experience.

Other Requirements

  • Experience and knowledge of communication standards (such as Ethernet, TCP/IP, OTN).
  • Solid understanding of timing protocols, such as IEEE 1588.
  • Experience with timing distribution in communications networks.
  • Experience with Timing Senstive Networks.
  • Excellent written and verbal communication skills.

Other Desired

  • Expertise in digital design languages: System Verilog, and VHDL.
  • Expertise with SW development languages C/C++, Python.
  • Experience with Xilinx tools and flow.
Share:
Refer to the Talent Network

Similar Jobs

Video Codec Architect

Waterloo, Canada, Canada

Networking Timing Solution Architect

Waterloo, Canada, Canada