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RTL Timing Engineer

160622
San Jose, CA, United States
Sep 14, 2021

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Job Description

Description

At Xilinx, we are leading the industry transformation to build an adaptable, intelligent world. ARE YOU bold, collaborative, and creative? We develop leaders and innovators who want to revolutionize the world of technology. We believe that by embracing diverse ideas, pushing boundaries, and working together as ONEXILINX, anything is possible.

Our culture of innovation began with the invention of the Field Programmable Gate Array (FPGA), and with the 2018 introduction of our Adaptive Compute Acceleration Platform (ACAP), has made a quantum leap in capability, solidifying our role as the adaptable platform supplier of choice. From the beginning, we have always believed in providing inventors with products and platforms that are infinitely adaptable. From self-driving cars, to world-record genome processing, to AI and big data, to the world's first 5G networks, we empower the world's builders and visionaries whose ideas solve every day problems and improve people's lives.

If you are PASSIONATE, ADAPTABLE, and INNOVATIVE, Xilinx is the right place for you! At Xilinx, we care deeply about creating significant development experiences while building a strong sense of belonging and connection. We champion an environment of empowered learning, wellness, community engagement, and recognition, so you can focus on work that matters - world class technology that improves the way we live and work. We are ONEXILINX.

 

Job Description

Xilinx is seeking an entry level professional to help RTL designers prepare their designs for backend implementation.  The candidate will be responsible for running quality checks on RTL and working with the RTL design team to clean metric dashboards.  The position requires a mix of EDA tool competence and TCL-based scripting capability.  The engineer will also be responsible for writing SDC constraints, synthesizing designs with Design Compiler, analyzing paths in PrimeTime, and driving front end timing closure.

 

#mh

 

Job Qualifications

 

Desired Tool Experience:

  • Synopsys: Primetime including SDC writing
  • Synopsys: Design Compiler

Optional Tool Experience:

  • Synopsys: Spyglass RTL LINT
  • Synopsys: Spyglass RTL DFT
  • Mentor: Questa CDC (Zero In)
  • Mentor: Questa RDC
  • Cadence: Conformal Low Power
  • Fishtail: Confirm

Shell Scripting Experience:

  • Proficient with scripting languages: TCL, Perl, and/or Python
  • Exposure to Cron and LSF job control automation

Experience and Education:

  • BS with 2+ years of exp or MS in Electrical Engineering or Computer Engineer or related equivalent

Highly motivated candidates with strong written and verbal communication skills and structured, well-organized work habits are encouraged to apply.

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