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SOC Design Engineer

160621
San Jose, CA, United States
Jul 27, 2021

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Job Description

Description

At Xilinx, we are leading the industry transformation to build an adaptable, intelligent world. ARE YOU bold, collaborative, and creative? At Xilinx, we hire and develop leaders and innovators who want to revolutionize the world of technology. We believe that by embracing diverse ideas, pushing boundaries, and working together as ONEXILINX, anything is possible.

Our culture of innovation began with the invention of the Field Programmable Gate Array (FPGA), and with the 2018 introduction of our Adaptive Compute Acceleration Platform (ACAP), has made a quantum leap in capability, solidifying our role as the adaptable platform supplier of choice. From the start, we have always believed in providing inventors with products and platforms that are infinitely adaptable. From self-driving cars, to world-record genome processing, to AI and big data, to the world's first 5G networks, we empower the world's builders and visionaries whose ideas solve every day problems and enhance people's lives.

If you are PASSIONATE, ADAPTABLE, and INNOVATIVE, Xilinx is the right place for you! At Xilinx we care deeply about creating meaningful development experiences while building a strong sense of belonging and connection. We foster an environment of empowered learning, wellness, community engagement, and recognition, so you can focus on work that matters - world class technology that improves the way we live and work. We are ONEXILINX.

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Job Description

We have an opening for an SOC Design Engineer in the SOC Design team. This team is responsible for designing the Processor Sub-system for the Adaptable Compute Acceleration Platform (ACAP).

In this role, you will:

  • Author design microarchitecture documents for SOC design blocks
  • Perform RTL Design for blocks in SOC to meet functional, timing, area and power requirements
  • Participate in reviews of design/documentation/quality-metrics
  • Execute quality checks on your design such as Lint, CDC, RDC
  • Participate in silicon bring-up for features owned
  • Implement Automation to increase yours and team's efficiency
  • Participate in build management

 

#mh

 

Job Qualifications

 

    • BS with 2+ years of exp or MS in Electrical Engineering or Computer Engineer or related equivalent
    • Excellent verbal and written communication skills
    • Understanding of physical design concepts (layout of place-and-route blocks, routing in metal layers etc)
    • Experience with Verilog RTL design
    • Simulation experience and experience building basic block level testbench
    • Familiarity with automation using scripting techniques such as PERL, Python or TCL
    • Familiarity with synthesis, static timing constraints, analysis & optimization
    • Ability to develop clear and concise engineering documentation
    • Familiarity with EDA tools from Cadence, Synopsys or Mentor
  • Bonus Qualifications
    • Understanding of ARM architecture and AMBA Protocols such as APB, AXI, ACE, CHI
    • Knowledge of designing multiple power domains including writing UPF
    • MBIST, LBIST, Scan, Scan Compression, ATPG and JTAG design
    • Experience in designing blocks for an SOC
    • Experience in integrating ASIC IP into SOC
    • Experience with FMEA and FMEDA
    • FPGA knowledge
    • Experience with Xilinx ISE or Vivado Design Suite
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