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Senior Design Engineer

160611
San Jose, CA, United States
Jun 8, 2021

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Job Description

Description

At Xilinx, we are leading the industry transformation to build an adaptable, intelligent world. ARE YOU bold, collaborative, and creative? We develop leaders and innovators who want to revolutionize the world of technology. We believe that by embracing diverse ideas, pushing boundaries, and working together as ONEXILINX, anything is possible.

Our culture of innovation began with the invention of the Field Programmable Gate Array (FPGA), and with the 2018 introduction of our Adaptive Compute Acceleration Platform (ACAP), has made a quantum leap in capability, solidifying our role as the adaptable platform supplier of choice. From the beginning, we have always believed in providing inventors with products and platforms that are infinitely adaptable. From self-driving cars, to world-record genome processing, to AI and big data, to the world's first 5G networks, we empower the world's builders and visionaries whose ideas solve every day problems and improve people's lives.

If you are PASSIONATE, ADAPTABLE, and INNOVATIVE, Xilinx is the right place for you! At Xilinx, we care deeply about creating significant development experiences while building a strong sense of belonging and connection. We champion an environment of empowered learning, wellness, community engagement, and recognition, so you can focus on work that matters - world class technology that improves the way we live and work. We are ONEXILINX.

Job Description

Xilinx is seeking a talented, motivated and self-driven RTL design engineer to be part of the Data Center Group (DCG) networking group. You will be taking part in design and implementation of high-performance networking designs and solutions, including those targeted for Xilinx 7nm ACAP.

Education Requirements

MS in Electrical Engineering or Computer Engineering with 3+ years relevant work experience, or bachelor’s degree in Electrical Engineering or Computer Engineering with 5 years relevant work experience.

Requirements and skills

Strong knowledge in following

  • Digital design and experience with RTL design in Verilog or SystemVerilog
  • FPGA/ASIC design flow, synthesis, timing analysis
  • Problem solving and debugging skills
  • Ability to communicate technical information in an organized and comprehensible manner
  • Fluent in working with Linux environment

Experience in following is highly desired

  • Scripting (TCL/Python/Perl, etc)
  • Verification techniques and flows
  • Knowledge of networking protocols, interfaces and standards like PCIe Gen3/4 and 100G Ethernet


 

 

 

 

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