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This is an exciting opportunity to work in the Xilinx SOC Verification Team as Senior Verification Engineer. The candidate will have an opportunity to work on state of the art verification environment using UVM verification methodology and C. The candidate will have opportunity to work on sub system level verification planning and execution
We are looking for candidates who have experience with verification of Soc
-Create block and Sub-system level verification plan, test plans .
-Develop block level test bench and tests in UVM methodology including scoreboard.
-Work on Sub-system level verification
-Work with designers to get the coverage closure
-Port the block level tests to full chip test bench
-Integrate VIPs as needed
-Work with software, validation and emulation teams as needed.
-Work on other aspects of verification like CDC, gate simulation.
-Work with silicon validation team on silicon bring up as needed
- BS with 12+ years of exp or MS with 8+ years of exp or PhD with 6+ years of exp in Electrical Engineering or Computer Engineer or related equivalent
-Prior experience in architecting and developing self-checking constrained random verification environment using System Verilog and UVM verification methodology.
-Execution of test plan, debugging failures, write functional coverage objects and review the code coverage and function coverage with design team
-Good understanding of object oriented programming concepts.
-Prior experience in verifying is system/sub system level involving multiple blocks.
- -Prior experience with protocols such as AXI, APB, AHB etc.
-Programming in scripting languages like Python, TCL and Perl.
-Excellent communication skills
-Good problem solving skills and analytical ability
-Familiarity with EDA tools for simulation, debugging, coverage analysis, CDC, LINT etc.
- Prior experience with PCIE Protocol
- Prior experience with Ethernet
-Understanding of ARM architecture and assembly language programming
-Understanding of I/O Virtualization Concepts.
-Prior experience in integrating Verification IPs (VIP) & UVC in verification environment.
-Prior experience in bringing up gate level simulation and debugging issues.
-Prior experience with dynamic CDC simulations.
-Understanding of FPGA architecture
-Experience with working on Serdes interfaces such as PCIE, Ethernet.
-Exposure to formal verification methodologies