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Xilinx Serdes Technology Group develops high-performance, multi-protocol wireline transceivers in state-of-the-art CMOS process. We are currently seeking an analog/mixed-signal design intern to join our world-class team.
The candidate will be responsible for the design of high-speed ADC-based receivers, DAC-based transmitters, or silicon photonics transceivers.
- Define circuit architectures optimized for high bandwidth electrical and optical links
- Perform link level simulation in Matlab and/or SPICE to prove the architecture
- Perform design and modeling of on-die RF passive components (e.g., inductors and capacitors) and/or optical structures
- Design circuit components (e.g., DAC, SAR-ADC, S/H, Analog Front-End, PLL, reference generation, clock distribution) required to implement the architecture in advanced FinFET process
Years of Experience
BS with 8+ years of exp or MS with 6+ years of exp or PhD with 3+ years of exp in Electrical Engineering or Computer Engineering or related equivalent.
Successful candidate needs to demonstrate the following