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Xilinx is currently looking for a dynamic individual to work within the Processor Systems Design and Verification Group on the next-generation SOC ASIC design. The individual will manage and contribute to the architecture and implementation of the verification test bench using System Verilog and UVM. This individual will work closely with designers to develop a testplan and a stand-alone methodology that is easily portable and reusable within the system testbench. The individual needs to work with teams who are in different geographical areas.
Responsibilities include the following:
· Work with Architecture, design, emulation and application teams and contribute to the verification of the next generation of SoC
· Play a key role in the development of verification environemnt in System Verilog/UVM
· Verify the architecture and performance of the design
· Work with Architecture and Emulation teams to ensure micro-architecture and design is fully verified/validated
· Develop comprehensive verification plan and drive the implementation of verification test cases, measure code coverage
· Strong analytical problem solving, and attention to details
· Strong experience in HDL, verification, and general computational logic design/verification concepts
· Expertise in Verilog/System Verilog, UVM, Scripting languages like Perl/Python, etc.
· Excellent written and verbal communication skills
· Excellent interpersonal skills, self-motivated
· Knowledge on ARM processor is a plus
Education Requirements : B.E or M.Tech
Years of Experience : 3 years