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Senior Design Engineer Manager

160572
Hyderabad, India, India
Aug 4, 2021

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Job Description

Description

At Xilinx, we are leading the industry transformation to build an adaptable, intelligent world. ARE YOU bold, collaborative, and creative? We develop leaders and innovators who want to revolutionize the world of technology. We believe that by embracing diverse ideas, pushing boundaries, and working together as ONEXILINX, anything is possible.
Our culture of innovation began with the invention of the Field Programmable Gate Array (FPGA), and with the 2018 introduction of our Adaptive Compute Acceleration Platform (ACAP), has made a quantum leap in capability, solidifying our role as the adaptable platform supplier of choice. From the beginning, we have always believed in providing inventors with products and platforms that are infinitely adaptable. From self-driving cars, to world-record genome processing, to AI and big data, to the world's first 5G networks, we empower the world's builders and visionaries whose ideas solve every day problems and improve people's lives.
If you are PASSIONATE, ADAPTABLE, and INNOVATIVE, Xilinx is the right place for you! At Xilinx, we care deeply about creating significant development experiences while building a strong sense of belonging and connection. We champion an environment of empowered learning, wellness, community engagement, and recognition, so you can focus on work that matters - world class technology that improves the way we live and work. We are ONEXILINX.

This position reports into the IP development group of the Data Center BU, one of the fastest growing units of XIilinx, chartered with the development of high speed networking and storage technologies. You will have the opportunity to build, develop and contribute to next generation IP in the areas of, DMA Engines, Security Engines (encryption, Decryption), PCIE, RDMA, NVMe etc. at speeds beyond 200 Gbps and be part of an exciting and vibrant team.

Minimum Required Qualification 

  • Masters/ Bachelors in EE/EC/CS with 15-20 years of experience in RTL Design
  • Solid understanding of ASIC design flows at latest process nodes
  • Experience in Digital design is a must with understanding of complete end to end from Specification to Tapeout
  • Experience working with Architecture teams and defining, writing product specifications and microarchitectural documents a must
  • Reviewing design and working with validation and verification teams to meet Pre silicon quality standards
  • Knowledge of FPGA design methodology is desirable
  • Knowledge of IP design with tradeoff of area, power and performance strongly desirable
  • Knowledge of protocols like PCIe, Ethernet, NVME, RDMA is added advantage
  • Excellent communication, problem solving and analytical skills

Education Requirements

  • Masters/ Bachelors in EE/EC/CS


Years of Experience

  • 15+ years of experience in RTL Design

Education Requirements

Years of Experience
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