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Physical Verification CAD Engineer

160467
Hyderabad, India, India
Jun 11, 2021

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Job Description

Description

At Xilinx, we are leading the industry transformation to build an adaptable, intelligent world. ARE YOU bold, collaborative, and creative? We develop leaders and innovators who want to revolutionize the world of technology. We believe that by embracing diverse ideas, pushing boundaries, and working together as ONEXILINX, anything is possible.

Our culture of innovation began with the invention of the Field Programmable Gate Array (FPGA), and with the 2018 introduction of our Adaptive Compute Acceleration Platform (ACAP), has made a quantum leap in capability, solidifying our role as the adaptable platform supplier of choice. From the beginning, we have always believed in providing inventors with products and platforms that are infinitely adaptable. From self-driving cars, to world-record genome processing, to AI and big data, to the world's first 5G networks, we empower the world's builders and visionaries whose ideas solve every day problems and improve people's lives.

If you are PASSIONATE, ADAPTABLE, and INNOVATIVE, Xilinx is the right place for you! At Xilinx, we care deeply about creating significant development experiences while building a strong sense of belonging and connection. We champion an environment of empowered learning, wellness, community engagement, and recognition, so you can focus on work that matters - world class technology that improves the way we live and work. We are ONEXILINX.

Xilinx is seeking a CAD Engineer who has some experience in the physical verification domain primarily with Calibre LVS/DRC and StarRC extraction tools. The candidate will need to write Perl/Python/Tcl scripts to automate various components of the verification process and improve the overall user experience.

Responsibilities:

  • Setup and support Calibre LVS/DRC PDKs
  • Develop Perl/Python/Tcl scripts to automate physical verification process and improve user experience
  • Work with EDA vendors and peers to debug tool and PDK related issues
  • Support global design community on custom design and physical verification CAD flows
  • Create and maintain physical verification regression testcases and test suites

 

Job Requirements:

  • Hands on experience in Calibre (LVS/DRC)
  • Hands on experience in Cadence Virtuoso
  • Familiarity with StarRC for parasitic extraction a plus
  • Experience in programming languages: Perl, Python, Tcl
  • Familiar with IC circuit design and function
  • B.Tech/B.E./M.Tech in Electrical/Electronics Engineering with 4-6 years experience
  • Self-motivated engineer must be able to anticipate problems and devise effective solutions
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