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Contractor - Senior Circuit Design Engineer

160471
San Jose, CA, United States
Jun 16, 2021

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Job Description

Description

At Xilinx, we are leading the industry transformation to build an adaptable, intelligent world. ARE YOU bold, collaborative, and creative? We develop leaders and innovators who want to revolutionize the world of technology. We believe that by embracing diverse ideas, pushing boundaries, and working together as ONEXILINX, anything is possible.

Our culture of innovation began with the invention of the Field Programmable Gate Array (FPGA), and with the 2018 introduction of our Adaptive Compute Acceleration Platform (ACAP), has made a quantum leap in capability, solidifying our role as the adaptable platform supplier of choice. From the beginning, we have always believed in providing inventors with products and platforms that are infinitely adaptable. From self-driving cars, to world-record genome processing, to AI and big data, to the world's first 5G networks, we empower the world's builders and visionaries whose ideas solve every day problems and improve people's lives.

If you are PASSIONATE, ADAPTABLE, and INNOVATIVE, Xilinx is the right place for you! At Xilinx, we care deeply about creating significant development experiences while building a strong sense of belonging and connection. We champion an environment of empowered learning, wellness, community engagement, and recognition, so you can focus on work that matters - world class technology that improves the way we live and work. We are ONEXILINX.

We are looking for a temporary contractor to design 300MHz IO circuits and clock generation/distribution circuits using 90nm CMOS technology.  Besides designing the circuits, this engineer will also be responsible for running circuit simulations to verify that the circuits meet specifications and working with layout designers to lay out the circuits.

In addition, this contractor will support other team members in analog circuit verification and chip-level timing verification checks.

 

Work hours: Monday to Friday, 9am to 5pm California time.

Duration: 12 weeks (with possibility of extending to 13 weeks)

Start date: First week of June, 2021

  • Minimum of MSEE with more than 5 years of industry experience in circuit design.
  • Must have hands-on experience in circuit design and have successfully designed/verified IO and analog circuits.
  • Must have experience working with layout designers to implement circuits.
  • Able to work independently and as a team.
  • Familiar with commonly used EDA tools, circuit simulators e.g. SPICE.
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