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As a member of the SoC Physical Integration team, you'll interface with various engineering groups, including architecture, design, CAD, software, and product engineering, across various geographies to work towards the physical/electrical verification and tape out of Xilinx SoC FPGA/ACAP devices. Common essential duties and responsibilities include, but are not limited to:
- Defining and developing flows and methodologies for chip level integration
- Developing tools for design verification or efficiency
- Designing (RTL and custom), verifying, and integrating FPGA/ACAP sub-blocks
- Coordinating activities between different design groups to ensure smooth integration
- Executing chip level physical verification
- Executing chip level electrical verification
- Basic understanding of FPGA architecture
- Knowledge of and/or experience with design and verification tools such as Virtuoso and Calibre
- Knowledge of and/or experience with P&R tools
- Fundamental circuit design knowledge including simulation experience with Spice and Verilog
- Strong debug skills
- Scripting experience using Perl, Python, TCL, C-shell, Make and/or other scripting languages
- Knowledge and experience with basic Unix data management and job control
- Excellent written and oral communication skills
BS with 2+ years of exp or MS in Electrical Engineering or Computer Engineering or related equivalent