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Staff ASIC Design Engineer-AI Engine

160257
San Jose, CA, United States
Jun 11, 2021

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Job Description

Description

At Xilinx, we are leading the industry transformation to build an adaptable, intelligent world. ARE YOU bold, collaborative, and creative? We develop leaders and innovators who want to revolutionize the world of technology. We believe that by embracing diverse ideas, pushing boundaries, and working together as ONEXILINX, anything is possible.

Our culture of innovation began with the invention of the Field Programmable Gate Array (FPGA), and with the 2018 introduction of our Adaptive Compute Acceleration Platform (ACAP), has made a quantum leap in capability, solidifying our role as the adaptable platform supplier of choice. From the beginning, we have always believed in providing inventors with products and platforms that are infinitely adaptable. From self-driving cars, to world-record genome processing, to AI and big data, to the world's first 5G networks, we empower the world's builders and visionaries whose ideas solve every day problems and improve people's lives.

If you are PASSIONATE, ADAPTABLE, and INNOVATIVE, Xilinx is the right place for you! At Xilinx, we care deeply about creating significant development experiences while building a strong sense of belonging and connection. We champion an environment of empowered learning, wellness, community engagement, and recognition, so you can focus on work that matters - world class technology that improves the way we live and work. We are ONEXILINX.

Job Description

Xilinx is seeking a capable and motivated RTL/ASIC design engineer to be part of front end design team of next generation AI Engine/ML processors. You will be take part in design and implementation of high-performance, low-power processor and accelerator IP for AI/ML applications.

Job Responsibilities

  • Define and specify micro-architecture of processor building blocks based on architecture requirements
  • RTL design and debug of complex blocks in Verilog / System Verilog
  • Analyze performance and make implementation choices to optimize timing
  • Analyze and optimize design for power efficiency and power integrity
  • Work with verificaton and physical design teams to achieve high quality design and successful tapeout
  • Solve customer problems through innovative enhancements to product architecture/ micro-architecture

 

Education Requirements

  • BSEE or equivalent and 8 years of relevant work experience, or MSEE or equivalent with 6 years of experience

Requirements

  • Strong knowledge in following
    • ASIC design flow and direct experience with ASIC design in sub-20nm technology nodes
    • Digital design and experience with RTL design in Verilog/SystemVerilog
    • Circuit timing/STA, and practical experience with PrimeTime or equivalent tools
    • Low power digital design and analysis
  • Experience in following is highly desired
    • Understanding of FPGA architecture and implementation flow
    • Modern SOC tools including Spyglass, Questa CDC, Cadence Conformal, VCS simulation
    • TCL, Perl, Python scripting
    • Version control systems such as Perforce, ICManage or Git
  • Strong verbal and written communication skills
  • Ability to organize and present complex technical information
  • Fluent in working with Linux environment

 

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