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Staff ASIC/FPGA Design Verification Engineer

160057
Singapore, Singapore, Singapore
Jul 2, 2021

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Job Description

Description

At Xilinx, we are leading the industry transformation to build an adaptable, intelligent world. ARE YOU bold, collaborative, and creative? We develop leaders and innovators who want to revolutionize the world of technology. We believe that by embracing diverse ideas, pushing boundaries, and working together as ONEXILINX, anything is possible.

Our culture of innovation began with the invention of the Field Programmable Gate Array (FPGA), and with the 2018 introduction of our Adaptive Compute Acceleration Platform (ACAP), has made a quantum leap in capability, solidifying our role as the adaptable platform supplier of choice. From the beginning, we have always believed in providing inventors with products and platforms that are infinitely adaptable. From self-driving cars, to world-record genome processing, to AI and big data, to the world's first 5G networks, we empower the world's builders and visionaries whose ideas solve every day problems and improve people's lives.

If you are PASSIONATE, ADAPTABLE, and INNOVATIVE, Xilinx is the right place for you! At Xilinx, we care deeply about creating significant development experiences while building a strong sense of belonging and connection. We champion an environment of empowered learning, wellness, community engagement, and recognition, so you can focus on work that matters - world class technology that improves the way we live and work. We are ONEXILINX.

Xilinx is looking for a talented individual to join the Wired IP Solutions Group (WISG) in the position of Staff ASIC/FPGA Design Verification Engineer. The successful candidate will join our design verification team developing ASIC and FPGA-based intellectual property (IP) to address the needs of state-of-the-art wired communications systems.

 

It is expected that the candidate will be an expert in Verilog coding and have in-depth knowledge or advanced verification methodologies such as constraint-random or UVM.  Working knowledge of RTL design and processes would be an asset, as would experience with scripting languages such as Perl and TCL.  It would also be desirable for applicants to have experience with wired communications protocols..

 

The successful candidate will have demonstrated their technical skill through extensive experience delivering ASIC and/or FPGA solutions to the market, and leverage this experience to architect innovative, high quality verification testbenches for complex IP products.

 

In addition to strong technical abilities, the position requires excellent written and verbal communication skills that will be utilized for multi-location collaboration, and developing verification specifications and test plans.  A desire to mentor and coach junior engineers would be a plus.

 

We are building the next generation Internet.  Xilinx already holds a leading position in the wired infrastructure manufacturing industry and is technologically well positioned to drive the ‘programmable imperative’ into all areas of advanced networking systems. This job opening presents an opportunity to work with a highly motivated team, best-in-class configurable silicon and software and industry leading wired communications technologies.

 

 

Requirements:

  • BSEE or B.Sc minimum required.
  • +10 years experience in  ASIC/FPGA verification 
  • Extensive experience in designing and implementing testbenches, coverage closure techniques and regression management flows
  • In-depth knowledge of modern verification practices including System Verilog, UVM and assertion based test
  • Experience and knowledge of communications standards (such as Ethernet, OTN, Interlaken)
  • Excellent written and verbal communication skills.

Desired:

  • Experience verifying digital communication systems (examples would include Ethernet, optical communications, and packet processing applications)
  • Experience with Xilinx tools and flow 

 

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