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Be part of Xilinx’s analog/mixed signal IP design team responsible for the design and development of next generation IOs, high speed memory (LPDDR5, DDR5, gDDR6, HBM2/HBM3, …) and chip-to-chip Gbps proprietary PHY IP solutions.
The candidate will be
Requirements for this position include:
1) 5-8 years of experience in AMS IP characterization and release of different design views.
2) Expert level in generating IBIS models for complex highly programmable multi-supply GPIOs and high speed IOs.
3) Familiarity with running ADS and Hyperlynx simulations to validate and compare IBIS models.
4) Hardware (Silicon) correlation and debug of IBIS models.
5) Basic understanding of functionality of different blocks in high-speed IO in order to model them correctly.
6) Hands on experience in using various simulation tools such as Liberate-AMS, Primetime, Nanotime, HSPICE, Spectre etc.,
7) Ability to quickly ramp up on existing script-based Xilinx in-house methodologies and flows.
8) Ability to handle multiple IP’s at the same time and deliver with highest quality.
9) Strong scripting skills using languages such PERL, TCL, Python etc.,
10) Excellent written and verbal communication skills especially cross geographic interaction with overseas teams.
11) Exhibit strong initiative and ownership of tasks and responsibilities with an open mind to contribute to any area/project.
12) Good attitude towards problem solving.
Education Requirements ME or MTech or Equivalent
Years of Experience 5-8years