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Architecture Engineer Intern

Longmont, CO, United States
Feb 26, 2021


Job Description


Xilinx develops highly flexible and adaptive processing platforms that enable rapid innovation across a variety of technologies - from the endpoint to the edge to the cloud. Xilinx is the inventor of the FPGA, hardware programmable SoCs and the ACAP (Adaptive Compute Acceleration Platform), designed to deliver the most dynamic processor technology in the industry and enable the adaptable, intelligent and connected world of the future in a multitude of markets including Data Center (Compute, Storage and Networking); Wireless/5G and Wired Communications; Automotive/ADAS; Emulation & Prototyping; Aerospace & Defense; Industrial Scientific & Medical, and others. Xilinx's core strengths simultaneously address major industry trends including the explosion of data, heterogeneous computing after Moore's Law, and the dawn of artificial intelligence (AI). 


The Xilinx FPGA Architecture group is seeking a dynamic architecture engineer (intern), based in San Jose, CA. The candidate will be involved in architecture design, verification and analysis, hardware modelling and system integration, system-level simulation and prototyping, performance validation, and/or architectural trade-off analysis. This is an ideal position for a would-be engineer with a keen interest in computer architecture, machine learning accelerators and FPGA architecture.


Job Description includes:

  • SoC architecture design, verification and analysis
  • Hardware modelling and system integration
  • System-level simulation and prototyping
  • Performance validation
  • Architectural trade-offs analysis
Job Requirements
  • Strong analytical problem solving, and attention to details
  • Knowledge of C/C++, Python programming and hardware modelling (Verilog/SystemC)
  • Knowledge of Linux and hardware design tools (Vivado Deisgn Suite, SDx)
  • Knowledge of Processor, on-chip networks and FPGA/SoC architecture
  • Knowledge of Machine Learning (ML) accelerators and systolic array architectures is a plus
  • Good written and verbal communication







Education Requirements

- Student currently pursuing a Master's degree or PhD in Electrical Engineering, Computer Engineering or equivalent field

-The expected start date is Aug/Sept 2021

-Duration of the internship is for 4 months, full-time (40 hours per week)

Refer to the Talent Network

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