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Xilinx's Vivado Simulator is a full feature compile code simulator available to all Xilinx users. It supports all commonly used HDL languages including Verilog, VHDL, System Verilog, System-C and design that is developed mixing these languages. The simulator has full UVM support has TCL frontend, Waveform Viewer and integrated debugger.
As part of refactoring and performance improvement the Simulator, it’s backend is being rewritten utilizing LLVM. The intern will work with a dedicated team to generate simulation Kernel for various Verilog/VHDL constructs using LLVM.
Roles and Responsibilities:
As a part of this role the candidate's responsibility includes
Looking for a candidate currently pursuing a B.S, M.S or Ph.D. in CS/CE/EE with project work in Compiler using LLVM.
Understanding of Hardware Description Language will be preferred.
This internship will be a minimum of 3 months to a maximum of 6 months, full-time (40 hours per week)
Expected start date is May/June 2021