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Design Manager - SoC Integration

159821
San Jose, CA, United States
Feb 9, 2021

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Job Description

Description

At Xilinx, we are leading the industry transformation to build an adaptable, intelligent world. ARE YOU bold, collaborative, and creative? We develop leaders and innovators who want to revolutionize the world of technology. We believe that by embracing diverse ideas, pushing boundaries, and working together as ONEXILINX, anything is possible.

Our culture of innovation began with the invention of the Field Programmable Gate Array (FPGA), and with the 2018 introduction of our Adaptive Compute Acceleration Platform (ACAP), has made a quantum leap in capability, solidifying our role as the adaptable platform supplier of choice. From the beginning, we have always believed in providing inventors with products and platforms that are infinitely adaptable. From self-driving cars, to world-record genome processing, to AI and big data, to the world's first 5G networks, we empower the world's builders and visionaries whose ideas solve every day problems and improve people's lives.

If you are PASSIONATE, ADAPTABLE, and INNOVATIVE, Xilinx is the right place for you! At Xilinx, we care deeply about creating significant development experiences while building a strong sense of belonging and connection. We champion an environment of empowered learning, wellness, community engagement, and recognition, so you can focus on work that matters - world class technology that improves the way we live and work. We are ONEXILINX.

As a technical manager on the SoC Physical Integration team, you'll work with and manage a team of engineers primarily on full chip EMIR (electromigration/IR drop) exeuction/methodology and secondarily on other physical integration deliverables.  Responsibliites include but are not limited to the following:
 

Job Description

As a technical manager on the SoC Physical Integration team, you'll work with and manage a small team of engineers primarily on full chip EMIR (electromigration/IR drop) execution/methodology and secondarily on other physical integration deliverables.  Responsibilities include, but are not limited to, the following:

 

  • Leading EMIR team to sign off at block level (reviews) and chip level (execution)
  • Participating in planning and scheduling of projects and driving team to deliver to set milestones
  • Assisting in defining EMIR methodology
  • Improving EMIR flows and processes to increase efficiency and productivity
  • Interfacing with design groups, CAD team, and tool vendors to ensure quality of work, flows, processes, and tools
  • Coordinating, working with, and training cross-site integration team to ensure consistency of workflows/processes
  • Mentoring junior engineers
  • Owning or assisting with:
    • Chip assembly
    • Integration block deliveries (design and verification)
    • Chip level physical integration/verification and tape out

 

#mh

 

Job Qualifications

BSEE, MSEE, or equivalent with 7+ years of relevant experience

Strong design background with deep EMIR knowledge preferred

Strong debug skills

Good understanding of electrical, timing, physical and reliability issues in deep sub-micron processes

Previous management experience preferred but will consider candidates without management experience

Outstanding communication skills (both written and oral)

Must be a team player

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