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Senior Software Engineer 2

159661
Hyderabad, India, India
Apr 9, 2021

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Job Description

Description

Xilinx Hyderabad is looking for a self-motivated engineer to work on QoR analysis, timing closure for FPGAs. We are looking for smart, creative people who have a passion for solving complex problems.

The ideal candidate should have a strong background in RTL design using Verilog/VHDL and timing closure techniques with strong foundations in timing analysis & digital design. The candidate should have a solid understanding of timing constraints, RTL coding styles and applications.

At Xilinx, we are leading the industry transformation to build an adaptable, intelligent world. ARE YOU bold, collaborative, and creative? We develop leaders and innovators who want to revolutionize the world of technology. We believe that by embracing diverse ideas, pushing boundaries, and working together as ONEXILINX, anything is possible.

Our culture of innovation began with the invention of the Field Programmable Gate Array (FPGA), and with the 2018 introduction of our Adaptive Compute Acceleration Platform (ACAP), has made a quantum leap in capability, solidifying our role as the adaptable platform supplier of choice. From the beginning, we have always believed in providing inventors with products and platforms that are infinitely adaptable. From self-driving cars, to world-record genome processing, to AI and big data, to the world's first 5G networks, we empower the world's builders and visionaries whose ideas solve every day problems and improve people's lives.

If you are PASSIONATE, ADAPTABLE, and INNOVATIVE, Xilinx is the right place for you! At Xilinx, we care deeply about creating significant development experiences while building a strong sense of belonging and connection. We champion an environment of empowered learning, wellness, community engagement, and recognition, so you can focus on work that matters - world class technology that improves the way we live and work. We are ONEXILINX.

 

Required: 

  • BS or MS in EE or CE with 1+ years of experience in digital design and/or timing closure
  • Strong background in RTL design using Verilog/VHDL
  • Timing Constraints (SDC) & Static Timing Analysis
  • Strong understanding and usage of ASIC and/or FPGA software tool chain
  • Strong Digital Design Fundamentals and applications
  • Scripting language such as TCL, Perl or Python
  • Excellent problem solving skills and willingness to think outside the box
  • Excellent communication skills and experience working with global teams

 

Preferred: Exposure to any of these areas: 

  • System Level Design and performance measurement
  • Fundamentals of Synthesis, Placement and/or routing  algorithms
  • Ability to understand C/C++ Code
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