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- Develop and implement plans to synthesize, implement including Design-For-Test (DFT) and close timing on complex digital integrated circuits at the block, subsystem or device level (100K to 10M+ gates) which are coded in VHDL/Verilog.
- Work with various design groups across different disciplines (Logic, Circuits, DFT & Layout) to meet timing closure, area, power, and performance requirements.
- Design, implement and maintain synthesis, DFT and Static Timing Analysis scripts using best-in-class methodologies.
- Analyze log and report files to ensure the tools are getting the required results and make adjustments to the scripts to get the required results within the scheduled milestones.
- Communicate regularly with the project teams world-wide to resolve issues and to ensure meeting targeted goals and schedule.
- Provide/propose new/enhance synthesis, DFT and STA flow and methodology to reduce the development TAT to meet product requirements.
- Bachelor/Masters Degree in Electrical/Computer Engineering
- Minimum 6 years of relevant experience
- Good experience and knowledge in design flow from Netlist to GDS, Floor Plan, Synthesis, route , STA, CTS, RC Extraction and correlation
- Static timing analysis, power and noise analysis and back-end verification across multiple projects.
- Proficient with backend design EDA tools Synopsys (preferred) or Cadence
- Experienced in Design-For-Test tools (Tetramax, DFT Advisor) & methodologies (Scan chains, ATPG, BIST, Fault models, Fault Coverage and generation).
- Proficient in RTL design using verilog
- Successfully track records of taping out complex SOC in 16nm and beyond.
- Working knowledge of deep sub-micron routing issues as they relate to power and timing.
- Strong scripting skills in Perl, TCL and Shell, particularly in synthesis & timing analysis
- Self-motivated team worker, good verbal and written communication skills