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Timing Methodology and Signoff Engineer

159567
Hyderabad, India, India
Mar 25, 2021

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Job Description

Description

At Xilinx, we are leading the industry transformation to build an adaptable, intelligent world. ARE YOU bold, collaborative, and creative? We develop leaders and innovators who want to revolutionize the world of technology. We believe that by embracing diverse ideas, pushing boundaries, and working together as ONEXILINX, anything is possible.

Our culture of innovation began with the invention of the Field Programmable Gate Array (FPGA), and with the 2018 introduction of our Adaptive Compute Acceleration Platform (ACAP), has made a quantum leap in capability, solidifying our role as the adaptable platform supplier of choice. From the beginning, we have always believed in providing inventors with products and platforms that are infinitely adaptable. From self-driving cars, to world-record genome processing, to AI and big data, to the world's first 5G networks, we empower the world's builders and visionaries whose ideas solve every day problems and improve people's lives.

If you are PASSIONATE, ADAPTABLE, and INNOVATIVE, Xilinx is the right place for you! At Xilinx, we care deeply about creating significant development experiences while building a strong sense of belonging and connection. We champion an environment of empowered learning, wellness, community engagement, and recognition, so you can focus on work that matters - world class technology that improves the way we live and work. We are ONEXILINX.

JOB description:

• Own  execution and deliver Timing signoff for  Large subsystem / full chip STA 

• Develop timing methodologies to streamline execution and solve critical timing problems
• Debug timing constraint issues, make edits to fix them
• Achieving QOR goals , Debug timing QOR issues in primetime
• Timing, Noise ECO creation using PT ECO, Tweaker
• Executing floorplan based Large hierarchical designs / full chip synthesis of designs
• • Low Power cleanup/debug/fixes/suggestions
• Scan insertion
• Synthesis checklist clean up
• Deliverables to LEC/CLP/PNR/DFT

•  Executing Conformal *(includes LEC, CLP, ECO) and Formality  runs for multiple block level and top level design  

  Debug COnfomal issues, analyze LEC aborts, LP issuesand  suggest optimization options

Job requirements :

• Should be hands on expereince in full chip STA 
•  Should be hands on STA Flow experience 
• Should be hands on expereince in full chip synthesis , hierarchical synthesis
• Should be hands on low power synthesis
• Good flow understanding, scripting and Debug
• Must have knowledge on RTL reading, Synthesis optimization, SDC, clocking, low power (UPF) and DFT
• Should be hands on COnformal and Formality flow experience from RTL to Netlist 
• Must have LEC debugging skills - aborts, mapping rules, optimization options, UPF debug

 

Education Requirements

BE , MS or equivalent

Years of Experience

7+ yrs

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