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Senior Packaging Design Engineer

159540
Hyderabad, India, India
Jan 7, 2021

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Job Description

Description

At Xilinx, we are leading the industry transformation to build an adaptable, intelligent world. ARE YOU bold, collaborative, and creative? We develop leaders and innovators who want to revolutionize the world of technology. We believe that by embracing diverse ideas, pushing boundaries, and working together as ONEXILINX, anything is possible.

Our culture of innovation began with the invention of the Field Programmable Gate Array (FPGA), and with the 2018 introduction of our Adaptive Compute Acceleration Platform (ACAP), has made a quantum leap in capability, solidifying our role as the adaptable platform supplier of choice. From the beginning, we have always believed in providing inventors with products and platforms that are infinitely adaptable. From self-driving cars, to world-record genome processing, to AI and big data, to the world's first 5G networks, we empower the world's builders and visionaries whose ideas solve every day problems and improve people's lives.

If you are PASSIONATE, ADAPTABLE, and INNOVATIVE, Xilinx is the right place for you! At Xilinx, we care deeply about creating significant development experiences while building a strong sense of belonging and connection. We champion an environment of empowered learning, wellness, community engagement, and recognition, so you can focus on work that matters - world class technology that improves the way we live and work. We are ONEXILINX.

Job Description

In this key technical position, you will engage in the following undertakings, leveraging your package design expertise.

  • Design advanced and heterogeneous integration packages to meet/exceed package and system electrical and thermal performances
  • Develop new package solutions including pin-out definitions, DRC/DFX and stack-up requirements
  • Develop design automation and methodologies
  • Implement chip-package design flow and LVS verification
  • Provide packaging expertise to support succeeding processes: manufacturing, assembly, testing, reliability and VNC

Job requirements

  • Expertise in Cadence Allegro Package Designer, including constraints setup and design flow
  • Cadence skill programming experience is a plus
  • Experience in Cadence Allegro Sigrity/Clarity tools or other SI tools is a plus
  • Familiarity with IC design and verification tools such as Virtuoso, and Calibre; PCB design tools such as Allegro, and Xpedition; PCB/Package DFM tools such as Valor, and CAM350; Gerber/ODB++/GDSII conversion software such as Artwork; MCAD tool such as AutoCAD, and SolidWorks
  • Knowledge in SI/PI, SPICE, DDR, and SerDes channel modeling
  • Knowledge in stress and thermal modeling on microelectronics packaging
  • Knowledge in packaging assembly including 2.5D/3D, flipchip, WLP and wirebond
  • Knowledge in packaging substrate structures, and manufacturing processes and yield factors
  • Knowledge in microelectronics packaging testing reliability requirements
  • Good communication skills

Education Requirements

Bachelors with 4+ years or Masters in EE or related fields

Years of Experience

A minimum of 5 years of relevant experience in advanced package design

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