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Senior CAD Engineer

159502
San Jose, CA, United States
Dec 21, 2020

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Job Description

Description

At Xilinx, we are leading the industry transformation to build an adaptable, intelligent world. ARE YOU bold, collaborative, and creative? We develop leaders and innovators who want to revolutionize the world of technology. We believe that by embracing diverse ideas, pushing boundaries, and working together as ONEXILINX, anything is possible.

If you are PASSIONATE, ADAPTABLE, and INNOVATIVE, Xilinx is the right place for you! At Xilinx, we care deeply about creating significant development experiences while building a strong sense of belonging and connection. We champion an environment of empowered learning, wellness, community engagement, and recognition, so you can focus on work that matters - world class technology that improves the way we live and work. We are ONEXILINX.

 

Description

Looking for somebody to take ownership of CAD flows related to SOC-level chip construction. The ideal candidate should be comfortable with all stages of the chip design process -- including RTL, Netlisting, Construction (P&R and custom), Extraction, STA -- and should be comfortable debugging issues in any of those stages. For example, on any given day the candidate might be asked to trace pin mismatches in RTL, review design layout to root-cause broken parasitics in STA, and then run profiling on their perl & python scripts to optimize performance. The preferred candidate will also have some experience with design work to ensure robust debug skills.

Since this is a CAD role, the candidate must be comfortable with object-oriented programming and scripting languages. Both Perl and Python are required for this role, with greater emphasis on Perl for most tasks.

Finally, the candidate should be able to communicate effectively in a cross-functional role, possess strong organizational skills, and have a strong sense of teamwork. They should be enthusiastic about attacking a new problem every day and shouldn't be afraid of learning from each experience!

 

Job duties may include (but are not limited to):

  • Maintaining Perl-based CAD flows for SOC-level construction, along with point scripts written in Perl, TCL, Python
  • Running daily or weekly regressions to proactively identify tool/flow issues and to qualify new tool releases
  • Intensive debug to root-cause complex issues in either a design or CAD flow or EDA tool
  • Working with EDA tool vendors to drive bug-fixes and tool enhancements
  • Pioneering new CAD development on next-generation flows and tools related to the above topics

 

Job Requirements:

  • Familiar with all stages of the chip design process: RTL, Netlisting, Construction (P&R and custom), Extraction, STA, etc.
  • Experience with debugging design issues across all of these stages
  • Familiar with industry tools: Aprisa, ICC2, Virtuoso, SeaScape, PrimeTime
  • Familiar with design data formats: RTL, GDS, DEF, LEF, SPEF, Verilog, CDL
  • Familiar with object-oriented programming and scripting languages: Perl, Python, C-shell, Tcl
  • Highly detail-oriented
  • Excellent communication skills -- candidate should be open and proactive when seeking feedback with customers or discussing tool bugs with a vendor AE
  • MSEE with 5+ yrs experience

Education Requirements
MS in Electrical Engineering


Years of Experience

5+ yrs

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