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Senior Verification Engineer

159388
Hyderabad, India, India
Jan 13, 2021

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Job Description

Description

At Xilinx, we are leading the industry transformation to build an adaptable, intelligent world. ARE YOU bold, collaborative, and creative? We develop leaders and innovators who want to revolutionize the world of technology. We believe that by embracing diverse ideas, pushing boundaries, and working together as ONEXILINX, anything is possible.

Our culture of innovation began with the invention of the Field Programmable Gate Array (FPGA), and with the 2018 introduction of our Adaptive Compute Acceleration Platform (ACAP), has made a quantum leap in capability, solidifying our role as the adaptable platform supplier of choice. From the beginning, we have always believed in providing inventors with products and platforms that are infinitely adaptable. From self-driving cars, to world-record genome processing, to AI and big data, to the world's first 5G networks, we empower the world's builders and visionaries whose ideas solve every day problems and improve people's lives.

If you are PASSIONATE, ADAPTABLE, and INNOVATIVE, Xilinx is the right place for you! At Xilinx, we care deeply about creating significant development experiences while building a strong sense of belonging and connection. We champion an environment of empowered learning, wellness, community engagement, and recognition, so you can focus on work that matters - world class technology that improves the way we live and work. We are ONEXILINX.

The Silicon development team is looking for an senior verification engineer in Xilinx India, for the verification of next gen Adaptable SoC with focus on Cache coherency, Interconnect performance verification.

 

Responsibilities include the following:  

 

  • Work with Architecture, design, emulation and application teams and contribute to the performance verification of the next generation of Cache coherent MPSoCs.
  • Play a key role in the development of verification infrastructure in System Verilog/UVM including VIPs and utilization of Emulation/Prototyping platforms for verifying next generation SoCs.
  • Work closely with Architecture and Design teams to ensure various performance metrics like throughput, latency are fully verified, often involving design micro-architecture debug.
  • Be responsible for a comprehensive Performance verification plan and drive the implementation of verification test cases to cover Low latency traffic, Best effort, Isochronous QoS traffic at system level.
  • Development of models using SV-UVM or Perl/Python scripts to automate test generation, results analysis.

  • BS/MS in EE, CE, or CS
  • 5-8 years of experience in functional  verification of blocks and  processor subsystems
  • Experience in performance verification is preferable but not a requirement
  • Experience in specifying and developing checkers, UVM monitors and other verification infrastructure at block, system level.
  • Knowledge of system-level architecture including buses like AXI5/ACE5 interfaces and knowledge on memory controllers such as DDR4/LPDDR4 is a plus.
  • Experience in Cache coherent interconnects is strong plus.
  • Strong Expertise in Verilog/System Verilog, UVM. Hands on knowledge on TB automation using Scripting languages like Perl/Python, etc.
  • Development of delay models using SV-UVM or Python to augment system level TBs is strong plus.
  • Strong analytical problem solving, and attention to details 
  • Strong experience in HDL, verification, and general computational logic design/verification concepts.
  • Excellent written and verbal communication skills
  • Excellent interpersonal skills, self-motivated
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