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- Develop Block, Sub System and Full chip Verification Environment and Test benches using SystemVerilog and Universal Verification Methodology (UVM)
- Use simulation tools like Synopsys VCS, Cadence IES to test FPGA fabric and SoC
- Develop sequences, tests cases, checkers, scoreboards and implement functional coverage using System Verilog and UVM
- Manage Regressions, analyze coverage and debug failures using Verdi and DVE
- Utilize good understanding of state of the art verification techniques like constraint random and coverage driven verification.
- Develop Code to run on CPUs using programing/SW languages like C
- Manage regressions and extract coverage and regression data using tools like Perl or Python
- Create regressions and coverage reports and provide updates to the management
- Communicate with cross functional teams on technical issues and status updates
Bachelor's Degree w/ 5+ years or MS w/ 3+ years or PhD in Electrical Engineering, Computer Engineering, or Computer Science or related equivalent
- Requires proven track record in technical leadership. This includes planning, execution, tracking, verification closure, and delivery to programs.
- Requires strong experience with development of UVM, OVM, VMM and/or Verilog, System Verilog test benches for full chip testbench and usage of simulation tools/debug environments like Synopsys VCS, Cadence IES to test full chip FPGA fabric and SoCs.
- Requires strong understanding of state of the art of verification techniques, including assertion and metric-driven verification.
- Verification experience in MathEngine/DSP optimized for wireless applications, AXI, NoC, HBM, DDR4, PCIe verification is a plus.
- Verification experience in full chip verification is a plus.
- Familiarity with verification management tools as well as understanding of database management particularly as it pertains to regression management is a plus.
- Strong understanding of different phases of ASIC and/or full custom chip development is required.
- Experience with FPGA programming and software is a plus.
- Verification experience in PCIe, Processors, Graphics is a plus.
- Experience with formal property checking tools such as Cadence (IEV), Jasper, and Synopsys (Magellan) is a plus.
- Experience with gate level simulation, power verification, reset verification, contention checking, abstraction techniques is a plus.
- DFX/DFT and UPF/ power-ware - simulation experience is a plus