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PHY/PLL Senior RTL Design Engineer

159358
San Jose, CA, United States
Nov 18, 2020

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Job Description

Description

At Xilinx, we are leading the industry transformation to build an adaptable, intelligent world. ARE YOU bold, collaborative, and creative? We develop leaders and innovators who want to revolutionize the world of technology. We believe that by embracing diverse ideas, pushing boundaries, and working together as ONEXILINX, anything is possible.

Our culture of innovation began with the invention of the Field Programmable Gate Array (FPGA), and with the 2018 introduction of our Adaptive Compute Acceleration Platform (ACAP), has made a quantum leap in capability, solidifying our role as the adaptable platform supplier of choice. From the beginning, we have always believed in providing inventors with products and platforms that are infinitely adaptable. From self-driving cars, to world-record genome processing, to AI and big data, to the world's first 5G networks, we empower the world's builders and visionaries whose ideas solve every day problems and improve people's lives.

If you are PASSIONATE, ADAPTABLE, and INNOVATIVE, Xilinx is the right place for you! At Xilinx, we care deeply about creating significant development experiences while building a strong sense of belonging and connection. We champion an environment of empowered learning, wellness, community engagement, and recognition, so you can focus on work that matters - world class technology that improves the way we live and work. We are ONEXILINX.

Job Description

Be part of Xilinx's IP team responsible for R&D/design of next generation clocking/PLLs solutions, next generation IOs, high speed memory (LPDDR4/DDR4, LPDDR5/DDR5, gDDR6, HBM2/HBM3, …), chip-to-chip Gbps proprietary PHY IP solutions. Responsibilities include but not limited to:

 1. Be part of the IP team of next generation PHY/PLL IPs. Engage in design architecture to micro-architecture phase

 2. Participate in defining specification, testing and verification of the IP components.

 3. Perform RTL-level design, including micro-architectural definition, of the digital portions of the IP architecture

 4.  Work closely with methodology, PD teams to implement RTL design into GDSII.

 5. Drive design closure thru synthesis, static-timing analysis, logical equivalency checking. Help improve flows and scripts for such tasks

 6. Support post-silicon product bring-up and debug, and sign-off on test-plans and characterization reports.

 7. Design support for SOC/FPGA integration teams, system HW/SW teams, and global operations/manufacturing teams.

 8. Setup and analysis of lint, synthesis, timing closure and DFT coverage reports

 9. Define or participate in micro-architecture definition and drive for power, performance and area (PPA) targets/enhancements

 10. Influence the methodology on mixed signal IP flows on simulations, timing closure. Participate in establishing CAD and design methodologies for correct by construction designs.

 11. Support SOC/FPGA integration activities

 

#mh

Job Qualifications

  1. BS with 5+ years of exp. MS with 3+ years of exp or PhD in Electrical Engineering or Computer Engineering or related equivalent

 

  1. SerDes/DDRPHY/PLL IP Design for high performance, low power FPGA/SOC designs

 

  1. Good knowledge of industry standards and practices in PHY/PLL Digital Design workflows and methodologies

 

  1. Familiarity with basic FPGA/SoC Architecture, front-end SOC/Digital IPs design flows, including design, simulation, synthesis, and timing analysis/closure and sign-off.

 

  1. Demonstrated proficiency in Verilog and digital design.

 

  1. Expertise in some or all the following areas is beneficial:

 

 

    1. Experience in the design of digital circuits and components in RTL, building/own the top-level integration as well as in synthesis, timing closure, and power-optimization of digital designs. 

 

    1. SerDes/DDR PHY Design experience on high performance, low power FPGA/SOC designs

 

    1. Hands on experience on Lint/CDC, SDC ownership and qualification, Timing ECO iterations, debugging in mixed-signal simulation environment, etc. 

 

    1. Understanding of the mixed signal IP flow with modelling and simulation. 

 

    1. Soft/Hard IP core delivery and handoff.

 

    1. Experience coding within Verilog and/or System Verilog along with scripting languages such as Perl, Tcl, or Python.  work as part of design team on timing and functional fixes/ECOs

 

    1. Experience in cross interaction with verification, DFT and physical design teams. 

 

    1. DFT design and methodologies especially for Logic BIST.

 

 

  1. Work with IP lead, project-manager, system architects, IC designers and physical designers to guarantee quality/timely deliverables meeting project’s schedule and technical requirements

 

  1. Proven track record of on-time IP delivery to SOC teams and successfully taking designs to production

 

  1. Experience with back-end flows, especially place-and-route, is beneficial.

 

  1. Excellent verbal, and interpersonal communication skills.

 

  1. Excellent technical communications. Ability to produce technical documentation.

 

  1. Able to operate without direct supervision but also work cross-functionally, cross-geographies collaborating and be part of a multi-disciplinary team in a dynamic/fast paste environment.

 

  1. Exhibit strong initiative and ownership of tasks and responsibilities. Seek help proactively as well as share and pass on knowledge

 

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